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Silicon has proven to have a great potential as anode material in lithium-ion batteries due to its high theoretical electrochemical capacity. However, silicon anodes deteriorate quickly during cyclic charging and discharging, rendering them useless in only a few cycles [1]. This has been attributed to the stresses induced by the large volume change of the material during cycling. Numerous attempts have been made to reduce these stresses, e.g. by using nanoparticles, nanorods, nanowires, thin films and porous structures, with a varying degree of success [2, 3]. While using finely structured materials aids in the intercalation of lithium by reducing the necessary diffusion distance, it also has the unfortunate effect of greatly increasing the specific surface area of the silicon. When using nano-sized materials, silicon’s ability to form a thin and stable solid electrolyte interphase (SEI) therefore becomes increasingly important. There are a number of factors that have a large influence on the SEI formation, making the process notoriously difficult to analyze, but also makes it possible to manipulate. Coating silicon with different nitrides and oxides, e.g. TiN and TiO, have previously been shown to enhance the cycling stability and Coulombic efficiency of the material [4, 5]. In this project the effect of coating the surface of silicon thin films with a thin (< 4-5 nm) layer of silicon nitride is investigated, as well as the effect of varying the stoichiometry of the silicon nitride. By itself silicon nitride has been shown to function as a conversion electrode material, forming elemental silicon and lithium nitride during the initial cycle, with thin films exhibiting capacities of up to 1800 mAh/g [6]. 40 nm silicon thin films were deposited by PECVD on copper foil using silane as precursor. The nitride was formed by addition of ammonia to the gas flow in the late stages of the deposition, and different stoichiometries were obtained by changing the ratio of these gases. By varying the flow rate of ammonia, coatings with four different compositions were made; pure silicon (A), stoichiometric Si3N4(D) and two intermediate compositions (B and C). Three electrodes were punched from each of the resulting films and mounted in coin cells with lithium metal counter electrodes and cycled at a current rate of C/3 for 150 cycles. During cycling, all the cells exhibited an initial increase in capacity, peaking at close-to-theoretical capacity within 10-40 cycles before beginning a slow decline. The average charge capacity for each series after 50, 100 and 150 cycles is presented in the figure, showing that the capacity retention increases with increasing nitrogen content for series A, B and C, and then decreases for series D. This indicates that a nitrogen coating has a positive effect on the deterioration mechanisms of the electrode, and that this effect increases with increasing nitrogen content of the coating, as long as a stoichiometric nitride is not formed. 1. Kasavajjula, U., C. Wang, and A.J. Appleby, Nano-and bulk-silicon-based insertion anodes for lithium-ion secondary cells. Journal of Power Sources, 2007. 163(2): p. 1003-1039. 2. Wu, H. and Y. Cui, Designing nanostructured Si anodes for high energy lithium ion batteries. Nano Today, 2012. 7(5): p. 414-429. 3. Ge, M., et al., Scalable preparation of porous silicon nanoparticles and their application for lithium-ion battery anodes.Nano Research, 2013: p. 1-8. 4. Memarzadeh Lotfabad, E., et al., ALD TiO2 coated silicon nanowires for lithium ion battery anodes with enhanced cycling stability and coulombic efficiency. Physical chemistry chemical physics : PCCP, 2013. 15(32): p. 13646-57. 5. Kohandehghan, A., et al., Silicon nanowire lithium-ion battery anodes with ALD deposited TiN coatings demonstrate a major improvement in cycling performance. Journal of Materials Chemistry A, 2013. 1(41): p. 12850-12861. 6. Suzuki, N., et al., Silicon nitride thin film electrode for lithium-ion batteries. Journal of Power Sources, 2013. 231(0): p. 186-189.

In this paper, we have developed a stacked Pr2O3/SiOxNy gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high ION/IOFF current ratio. This phenomenon is attributed to the smooth Pr2O3/poly-Si interface and the low interface trap density provided by N2O plasma treatment. The presence of an SiOxNy buffer layer also enhanced the electrical reliability of the Pr2O3/poly-Si TFT. All of these results suggest that a high-k Pr2O3 gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.

We describe a novel, solid-phase crystallization method for synthesizing large-grained, textured silicon films on amorphous substrates at relatively low processing temperatures ( 10 μm) for films crystallized by the SSC method. Hall measurements conducted on boron-doped films, annealed at 800°C, showed excellent hole mobility with values exceeding 180 cm 2 /V s, which was almost a factor of six higher than that found in polycrystalline films obtained from standard annealing procedures (annealing temperature ∼600°C for 28 h).

INTRODUCTION. If such a Silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) technology, namely, high-performance single crystalline silicon (c-Si) MOSFETs formed locally at the required position at low temperature (150°C or less) on flexible substrates, were established, so-called “flexible electronics” could be further advanced. Moreover, this technology could also be applied to system integration, namely, simultaneously mounting different devices such as integrated circuits and sensors[1]. We have proposed a novel layer transfer of the (100)-oriented c-Si thin film to a flexible substrate at very low process temperature[2]. In this study, by applying above-mentioned technology, the performance of flexible MOSFETs fabricated by using a c-Si film transferred by meniscus force was verified experimentally. EXPERIMENTAL. The SOI layer [p-type Si(100), 10-30 W∙cm] was patterned to form a 3-µm-wide and 5-µm-long dog-bone shape with 20×20 µm2 square regions at both ends. This pattern is applicable to MOSFET fabrication to form a source, a channel, and a drain. To form supporting columns, holes with size of 2 × 2 µm2 were made at intervals of 3 µm in the square regions. The 300 nm-thick buried-oxide (BOX) layer was isotropically etched by 33% hydrofluoric acid at room temperature for 90 seconds by using the patterned SOI layer as a mask for the midair cavity. As a result of the etching of the BOX layer below the patterned SOI layer, the narrow SiO2 columns can be formed underneath both end regions of the film. Figure 1 schematically shows the meniscus force(F=πR 2 γ[(1/R)-(2cosθE/H)]+2πR2γ sinθE ) mediated layer transfer (MLT) of SOI layer to a flexible substrate[2]. The starting and counter PET substrates were in close face-to-face contact with the filling water, and these substrates were heated on a hot plate at 80°C. RESULTS AND DISCUSSION. When the starting SOI wafer and the PET substrate were separated, it was confirmed that the original form and position of the SOI layer were completely maintained after the film transfer. The electron-backscatter-diffraction (EBSD) pattern map confirms that a (100)-oriented c-Si thin film was successfully formed on PET substrate at 80°C. Here, to confirm the adaptability of this layer transfer technique to thin-film devices, MOSFET were fabricated on a PET substrate. The source and drain regions were implanted with phosphorus ions at a dosage of 1×1015 cm-2. To control the threshold voltage, boron ions were injected (at a dosage of 1×1011 cm-2) into the channel region. After impurities in the source, channel, and drain regions were activated by heating at 1000 ºC in nitrogen ambient for 10 minutes, the BOX layer was isotropically etched by 33% hydrofluoric acid at room temperature for 90 seconds by using the patterned SOI layer as a mask for the midair cavity. As a result of the etching of the BOX layer below the patterned SOI layer, the narrow SiO2 columns can be formed underneath both end regions of the film. Here, the key process is the thermal oxidation of the SOI layer on the midair cavity. An 11-nm-thick gate insulator was formed on a SOI wafer temperature at 1000 ºC in dry oxygen ambient for four minutes[3]. By thermally oxidizing the SOI layer, the SOI layer can be covered on both surfaces with SiO2. After that, the forming gas annealing was performed at 400 ºC in a 3%-hydrogen/nitrogen mixture for 30 min. The thermal oxidation and subsequent hydrogen anneal ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. After the SOI layer was transferred to the PET substrate by MLT technique, a 200-nm-thick SiO2 film was deposited at 130 ºC by remote plasma chemical vapor deposition (RPCVD). After the contact holes are opened, the gate, source, and drain electrodes are formed by aluminum evaporation and wet etching. The MOSFET dimensions are length (L) of 3.7 µm and width (W) of 3 µm, and the maximum temperature of the fabrication process is 130ºC. Figure 2 shows Id-Vg characteristics of the MOSFETs fabricated on a transferred Si film. The MOSFET dimensions are L = 3.7 µm and W = 3 µm. The MOSFET showed a mobility of 343 cm2V-1s-1. A CKNOWLEDGEMENTS.A part of this work was supported by Research Institute for Nanodevice and Bio Systems, Hiroshima University and Funding Program for Next Generation World-Leading Researchers (NEXT Program) from the Japan Society for the Promotion of Science (JSPS). This work was supported by JSPS KAKENHI Grant Number 252156. REFERENCES. [1] T. Fukushima, et. al., IEDM Tech. Dig., 1 (2008). [2] K. Sakaike el al., Jpn. J. Appl. Phys. 53, 018004 (2014). [3] K. Sakaike el al., Appl. Phys. Lett., 103, 233510 (2014).

The possibility of obtaining Si thin films by electrodeposition from the oxygen and water stable N-butyl-N-methyl-pyrrolidinium bis(trifluoromethyl-sulfonyl)amide ionic liquid at room temperature was investigated. The results obtained using SiCl4 and SiBr4 as precursors and aluminium and nickel as substrates were compared. Cyclic voltammetry, square wave voltammetry and chronoamperometry were used to characterize the electroreduction step of the silicon species. The results showed that the growth of the silicon layer is very slow, yielding only clusters of silicon at low cathodic potentials and short electrolysis times. At higher electrodeposition potentials and/or longer deposition times, the films became rougher and cracks appeared in the layers. This was mainly due to the accumulation of tensile strains during growth. The layers were very reactive to air and humidity, probably due to the high porosity of the film. In some cases, contamination of the layers by S and F was also observed

Layer-by-layer growth of single-crystalline Si with doping was achieved by a temperature-modulation (TM) method combined with an intermittent supply of Si 2 H 6 and dopant precursor B 2 H 6 for p-type growth on Si(100). B 2 H 6 was introduced at a predetermined timing of supply in several doping modes. This TM Si molecular layer epitaxy enabled the growth of a flat surface with layer-by-layer growth in a self-limiting manner on Si(100) and with an outstanding high carrier concentration of over 5 X 10 20 cm -3 while maintaining selective epitaxy at the maximum temperature of 470°C. Based on the results of doping in several modes of growth, the incorporation mechanism of dopant on the growing surface is discussed with respect to the TM process.