Search

The semiconductor ICT industry continues its neverending pursuit of new approaches for fabricating integrated circuits to reduce device cost and improve device performance. For future device generations, many different approaches are considered, for which the efficient engineering of new materials and architectures are the main challenge to improve device performance. InP is one of these new materials, which is considered to be used as virtual substrate for III-V based nMOS devices.

We discuss the selective epitaxial growth of InP on patterned Si (001) substrates with Shallow Trench Isolation using a thin Ge buffer to facilitate InP nucleation. The main focus is the defect formation mechanism during epitaxial growth and to develop solutions to reduce defect density so that device-quality III-V virtual substrates can be realized on large-scale Si substrates. We compare the InP growth on on-axis and off-axis Si substrates. In the case of off-axis wafers, the formation of stacking faults / twins cannot be avoided, at least not at one of the four STI side-walls. The formation of antiphase domain boundaries is reduced (but not yet completely eliminated) by engineering the local Ge surface profile. Further, the high density of Ge surface steps promotes step-flow growth mode instead of 3D growth during the growth of the InP seed layer. Finally, high aspect ratios (>2) allow to confine threading dislocations in the bottom of the trench.

Planar devices have been used for manufacturing integrated circuits for many decades already. Further device shrinkage and performance improvement by conventional size scaling are reaching their limits because of increasing difficulty to control short channel effects (SCE). In this paper, various approaches for source and drain doping in planar transistors are presented and discussed. The conventional approach based on implant and dopant activation anneal is analyzed versus other technologies. Especially many new developments in thermal treatment of the wafer in order to activate dopants and control their diffusion are presented.

This paper presents the benefits of both co-implantation of diffusion-retarding species and ultra-fast annealing techniques as studied on blanket and device wafers. F and C co-implantation with B+ for PMOS and P+ for NMOS combined with conventional spike annealing produce reduced junction depths and improved dopant activation and profile abruptness, as measured on blanket wafers and compared to similar implants without the co-implanted species. Device wafers show that the overlap capacitance is reduced, consistent with the shallower junction depths and reduced lateral diffusion. The improved dopant activation manifests itself in reduced series resistance and improved Ion values. Depending on the implant conditions, either the gate/extension overlap capacitance or the series resistance can be improved when sub-melt laser annealing is used instead of conventional spike anneal. For both approaches, scanning spreading resistance microscopy (SSRM) measurements confirm the shallow junction depths and reduced lateral diffusion.

not Available.

not Available.

In this work, we present the use of SSRM, an electrical characterization technique based on atomic resistance microscopy (AFM), as a verification tool for the accurate calibration of two dimensional (2D) process simulations on advanced high speed bipolar HBT devices with fT/fmax values exceeding 200GHz. The 2D HBT process simulator has been calibrated based on SIMS measurements and TEM pictures. The process simulations consider coupled diffusion of carbon and silicon point defects under several RTA conditions [1]. Kick-Out and Frank-Turnbull mechanisms model the carbon diffusion. Extended short-loop experiments under equilibrium and non-equilibrium conditions increased the accuracy of the simulations [2]. Lateral and vertical scaling of the bipolar device dimensions is an absolute requirement for obtaining current and power cutoff frequencies (fT, fmax) above 200GHz [3]. The state-of-the-art QSA HBT investigated in this work for instance has an enclosure of active area over the poly emitter of only 0.03μm. As the external base implantation, needed to obtain low base resistance, is done after the poly emitter patterning, a precise determination of the base collector junction becomes difficult but at the same time important, taking into account the interaction with the selectively implanted collector (SIC) and the importance of the base-collector junction location for the DC device characteristics. Simulations using the calibrated 2D-TCAD platform show the different shapes of the external base-collector metallurgical junction as a function of the poly emitter sidewall angle (fig 1). The vertical depth of the basecollector metallurgical junction along the STI drops from 90nm to 75nm and even 45nm for a poly emitter sidewall angle of respectively 90°, 80° and 73°. From crosssectional pictures we know that the poly emitter sidewall angle is around 80°, but so far we were unable to verify the exact position of the base-collector metallurgical junction on real silicon. A key advantage of the SSRM technique however is its capability to determine the precise location of electrical transistor junctions. The improvements in sample preparation and the introduction of full diamond probes have enabled a drastic increase of the spatial resolution down to 1-3nm [4,5], even for HBT transistors where many materials with different hardness are present (silicon, polysilicon, oxide, nitride, silicide, SiGe). Figures 2 and 3 show such SSRM plots for the QSA 0.13μm SiGe:C HBT. A comparison is shown with a 2DTCAD plot and with a TEM picture respectively. Geometrical distances and the base-collector junction can be clearly distinguished on the SSRM plots. A quantification of the key geometrical and electrical distances extracted from the SSRM data are summarized in table 1. They are compared with the TCAD values. SSRM quantifies correctly known geometrical values like for instance the nitride thickness of the emitter window and the oxide undercut under this nitride. The measured lateral and vertical electrical junction depths from SSRM correspond well with the values extracted from the calibrated 2D-TCAD platform. We conclude therefore that the 2D-TCAD process simulator is correctly calibrated. This TCAD platform will be used for future process optimization of advanced high speed HBT devices.

not Available.