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Introduction: In the past few years junctionless nanowire MOSFETs appeared as one of the candidates for future technological nodes having great potential in digital and analog applications [1,2]. In these devices the fin height (HFIN) and the fin width (WFIN) have a strong influence on the electrostatic coupling that in turn becomes important for the ION/IOFF ratio [3]. Fig.1 shows the cross-section of a junctionless nanowire transistor with its geometrical parameters. This work analyzes the effects of the fin height on the electrical parameters of junctionless transistors through experimentally calibrated 3-D simulations. Results show that for long channel devices the better compromise is obtained with higher fin height, with higher ION/IOFF and smaller values of SS and DIBL, whereas for short channel ones the better compromise is found with smaller fin height, due to the reduced SS and DIBL and increased ION/IOFF ratio. Results: To study the effect of the HFIN on these devices, simulations were made using Sentaurus TCAD from Synopsys. The simulations were calibrated with experimental data for long channel devices as a function of the WFIN and extrapolated for a study with variable HFIN. Fig. 2 shows the experimental and calibrated simulation for several WFIN as a function of the gate voltage with a drain voltage of 50mV [4]. The simulated devices used doping concentration of 4.1018 cm-3, Equivalent Oxide Thickness (EOT) of 1.38nm and work-function of 4.7eV. The box thickness of 150nm, WFIN of 13nm and 18nm, variable HFIN from 10nm to 60nm, channel length (LG) of 100nm, 50nm and 30nm and channel extensions of 30nm. The devices have either doped extensions with 5.1020cm-3 (to reduce the series resistance (RSD) [5]) or extensions with the same doping of the channel (referred as non-doped in this work). For these simulations, the crystallographic orientation of the device was considered and its effects on carrier mobility. Fig. 3 shows the subthreshold slope (SS) as a function of HFIN and one can see that doping the extension increase the SS for all devices, showing the degradation caused by short channel effects [6]. One can see that for long channel (LG=100nm), the SS decreases as HFIN is increased, while the opposite occurs to the short channel devices (LG=30nm), i.e. the HFIN reduction improves the SS. Fig. 4 shows the threshold voltage (VTH) and the DIBL as a function of HFIN. For devices tending to double-gate architecture (HFIN>>WFIN) the VTH is weakly sensitive to HFIN while for smaller HFIN the VTH increases due to the electrostatic coupling of the gate. The same occurs with the DIBL and the improvement on these devices comes from a smaller HFIN. Fig. 5 and Fig. 6 shows the On and Off currents (ION and IOFF, respectively) as a function of HFIN , respectively. The ION has been extracted at a gate voltage overdrive (VGT) of 0.8V and IOFF at VGT=-0.3 V. The ION values were compensated by the effect of the RSD. The use of doped extensions increase the ION, effect that is more pronounced on smaller HFIN and LG, whereas it induces a higher degradation on the IOFF for short LG than the long LG. The devices with non-doped extensions have better IOFF because of lower SS but the ION is much lower. Fig. 7 shows ION/IOFF ratio as a function of the HFIN . We can see that for LG=100nm a higher ION/IOFF ratio comes from the increase in HFIN while for LG=30nm the better ratio comes from the decrease in the HFIN. It indicates that the better ION/IOFF is obtained moving towards double-gate shape for long-channel devices to nanowire shape for short channel ones. Also, the LG=50nm has values close to LG=100nm, but for the doped extensions the device has tendency similar to the LG=30nm. Conclusions: For this work, we analyzed the main parameters of junctionless transistors with different HFIN and the effects for short LG with and without doped extensions shows a greater advantage with smaller HFIN (nanowire), while for long LG the advantage becomes more pronounced by the increase of HFIN as the device tends to become double gate. Acknowledgements: The authors acknowledge Sylvain Barraud, Maud Vinet and Olivier Faynot for providing the samples and the founding agencies CNPq, CAPES and FAPESP [grant #2016/10832-1]. References: [1] C.-W. Lee, et al. IEEE TED, 57,620-625,(2010). [2] R. T. Doria et al. IEEE TED, 58,2511-2519,(2011) [3] R. Yan et al. Microelectronics Reliability, 51,1166-1171,(2011). [4] T. A. Ribeiro, et al. 32nd SBMicro,1-4,(2017). [5] C.-H. Park et al, SSE, 73,7–10,(2012). [6] A. Cerdeira, et al. 30th SBMicro,1-4,(2015). Figure 1

With feature size of transistors reducing down to sub-20 nm nodes, high mobility channel materials and novel device structures are critical to further improve the performance of transistors. Junctionless nanowire transistor (JNT) is recently proposed and regarded as promising candidate structure due to its simple fabrication process and excellent electronic properties [1]. Germanium-on-insulator (GOI) substrate is regarded as promising substrate due to its advantages of both Ge and on-insulator substrates. Although GOI-based JNTs have been reported [2,3], the performances are far from satisfactory. In this work, we fabricated high performance GOI-based JNTs with much smaller dimensions, where channel length and width are both less than 100 nm, and demonstrated their fabrication process and electrical properties in detail. Fig.1 shows SEM images of tri-gate JNTs with different dimension, (a)W/L=40nm/70nm and (b) W/L=40nm/100nm, respectively. Fig.2 shows TEM image of a GOI sample with Tge=10 nm. The original thickness of Ge film was about 50 nm. We reduced Tge down to 10 nm using a simple wet retching method as reported in our previous work [4]. Fig.3 shows the schematic diagrams of fabrication process. To reduce costs and improve efficiency, we used both optical lithography (OL) and electron beam lithography (EBL). First, we used OL to define active region of the devices. GeO2 channel passivation was carried out by ozone oxidation at 300 °C for 30 min. Then EBL was carried out to define the channel and gate electrode, which had much smaller dimensions. Finally, we used OL and lift-off process to define measuring electrodes. Fig.4 (a) shows Id-Vg characteristics of JNTs with Tge =20nm and Tge=10nm, respectively. It can be observed that Ion/Ioff ratio of the JNT with Tge=10nm is larger than 105 at Vd= -1V. The subthreshold slope at Vd= -0.1V and the drain induced-barrier lowering (DIBL) are estimated to be 110 mV/dec and 140 mV/V, respectively. With decrease of Tge, we get better device performance. Fig.4 (b) shows the Id-Vd characteristics of JNT with W/L=40nm/70nm, Na=1018 cm-3 and Tge=10nm. Liner and saturation regions are clearly exhibited. Fig.5 (a) shows the influence of temperature on Id-Vg characteristics of JNTs with W/L=40nm/70nm, Na=1018cm-3 and Tge =10nm. It can be observed that with increase of temperature leakage current increased dramatically. Fig.5 (b) shows mobility of the same JNT. The reported mobility values of a GOI JNT with Na= 1019 cm−3 [2] and a conventional Si pMOSFET [5] are also plotted for comparison. The peak mobility is larger than 200 cm2V-1S-1, which is close to that of bulk germanium with a doping concentration of 1018 cm−3. In summary, we fabricated high performance GOI-based JNTs using a Si-compatible process which combines OL and EBL. Good Ion/Ioff ratio, subthreshold slope, DIBL and mobility are extracted, which indicating that ultra-thin body GOI-based JNTs are promising for high performance circuits. The device performance can be improved by optimizing the fabrication process and device structure. Acknowledgments: This work was supported in part by the National Natural Science Foundation of China (No. 61306105). [1] J. P. Colinge et.al, Nat. Nanotechnol. 5, 225, 2010. [2] D. D. Zhao et al. Jpn. J. Appl. Phys., Part 1, 51, 04DA03, 2012. [3] R. Yu et al., Phys. Status Solidi RRL 8, 65, 2014. [4] C. Sun et al. ECS Solid State Lett. 4, P43, 2015. [5] S. Takagi et al, IEEE Trans. Electron Devices, 41,2363, 1994. Figure 1

Recently, III-V semiconductor nanowires are widely explored as field effect transistor (FET) materials for the next generation high speed electronics. Further tuning the working mode of the nanowire FET is essential in the large scale device design and fabrication, which is still a significant challenging in the current moment. In this study, decoration of metal nanoparticles with different work functions can effectively tune the threshold (VTH) of III-V nanowire FETs. Specifically, high work function metals such as Au and Pt can shift VTH to the positive side while low work function metals such as Al can tune VTH to the negative side, for the typical InAs, InP and InGaAs NWFETs, by depleting electrons from and donating electrons to the III-V nanowire channels. Furthermore, the fabrication of inverters using the depletion and enhancement mode InAs NWFETs show the great potency of the metal decoration method in low-power and high performance electronic devices.

Junctionless nanowire transistors have a constant doping profile from source to drain, providing a great scalability without the need of rigorously controlled doping gradients and activation techniques. Therefore, these devices are considered as promising for decananometer era. This work proposes an analytical model for the drain current in junctionless nanowire transistor (JNT) accounting for short channel effects and temperature dependence. Tridimensional numerical simulations of p-type devices have been performed to validate the model. Experimental data of n-type devices have also been used.

Junctionless Nanowire transistors have been recently proposed as an alternative to overcome the short channel effect caused by the reduction of the transistors dimensions. These devices behave like a gated resistor due to the lack of the p-n junctions in the channel/ source and channel/drain regions. The influence of doping concentration, silicon width, silicon height and gate oxide thickness on the intrinsic gate capacitances are presented in this paper by using three-dimensional numerical simulations and experimental results of fabricated devices. Also the influence of the applied drain bias in the components of the intrinsic gate capacitances is addressed.

The series resistance (RS) of Junctionless Nanowire Transistors (JNTs) with different doping concentrations was extracted from 473 K down to 100 K. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices and the impact of the series resistance on the drain current of the devices was evaluated. The RS analysis was carried out through experimental results and devices tridimensional numerical simulations. According to the study, RS presents opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on RS is noted with the temperature increase, whereas a resistance decrease is obtained with the temperature lowering in IM devices. The parasitic resistance in JNTs affects the drain current in such a way that there may not be a Zero Temperature Coefficient (ZTC) operation point.

In this paper, we report on the fabrication and characterization of voltage-programmable (VP) nanowire (NW) field-effect-transistor (FET) devices suitable to enhance the flexibility in circuit design, such as of reconfigurable logic. Silicon NW-structures with mid-gap Schottky S/D junctions on silicon-on-insulator (SOI) substrate were fabricated performing as unipolar CMOS-like transistors. The desired device type, i.e. NMOS or PMOS, is programmed by application of a certain back-gate voltage. The programming capabilities of the devices fabricated using this approach are demonstrated experimentally using a VP-NW-CMOS inverter circuit on a multi-SOI-substrate like set-up.

We find that self-heating effects are not pronounced in silicon nanowire transistors with channel length 10 nm even in the presence of the wrap-around oxide. We observe a maximum current degradation of 6% for VG=VD=1.0 V in a structure in which the metal gates are far away from the channel. The overall small current degradation is attributed to the significant velocity overshoot effect in these structures. The lattice temperature profile show moderate temperature rise and velocity of the carriers is slightly deteriorated due to self-heating effects when compared to isothermal simulations.

I. Introduction In order to reduce the short channel effects, junctionless nanowire transistors (JNT) can be a very interesting option once it avoids the lateral diffusion of impurities from source and drain regions to the channel. In addition, as they are a multiple gate devices it is possible to improve the electrostatic control over the channel charges [1-4]. While the channel in state-of-art nFinFET devices is undoped or lightly doped with p-type impurities, n-type JNT have a uniform heavy concentration of donor impurities from source to drain, which simplifies the device fabrication, once it dispenses complicated annealing techniques [5-6]. A schematic view and a longitudinal-section of n-type JNT and FinFET devices are shown on Fig. 1. As demonstrated in Fig. 1 JNT and FinFET are made using Silicon-On-Insulator (SOI) substrates. The thermal resistance associated to the buried oxide is in order of 100 times larger than silicon. Thus, both device alternatives can suffer from the difficulty of dissipating the heating of the silicon film caused by the Joule effect thanks to the current conduction, the so-called self-heating effect (SHE). This paper aims at comparing the self-heating effects (SHE) between FinFET and JNT devices using three-dimensional simulation. II. Devices Characteristics The comparison of SHE between JNT and FinFET devices by means of three-dimensional numerical simulations has been performed with Synopsys Sentaurus Device simulator [10]. Both JNT and FinFET devices have been simulated with gate oxide thickness of 2nm, channel length (L) of 0.5 µm and 1 µm, fin width (Wfin ) of 10 nm and 20nm, fin height (Hfin ) of 60 nm and 10nm. For the JNT P+ polysilicon was used as gate material. The JNT has been doped uniformly with 5x1018 cm-3 and 1x1019 cm-3 with n-type impurities, while the channel region of FinFET has been doped with 1x1015 cm-3with p-type impurities. In order to avoid the series resistance, the drain and source extensions were simulated with 5nm. The buried oxide thickness is 100 nm. The simulations have been done with isothermal grid at 300K where there is no self-heating effect (hereafter mentioned as without SHE) as well as with thermal contact at the buried oxide allowing the thermal generation to be accounted in the several grid points (hereafter mentioned as with SHE). III. Results and analysis Fig.2 and Fig. 3 present the behavior of the drain current as a function of gate voltage for FinFET and JNT. It is possible to compare the simulations with and without SHE, which present the same behavior i.e., there is no clear SHE due to the lower VD (50mV) resulting in lower static power (P = VD.ID ). According to the results obtained for lower VD, it is possible to confirm that those simulations are calibrated for analysis with higher VD values since their behavior are the same, independently if accounting or not the silicon film heating. On the other hand, when the VD increased to 1.5V, it is clearly visible the presence of the SHE in both JNT and FinFET as the current with non-isothermal grid is smaller than with isothermal one, thanks to the mobility degradation due to temperature rise. Finally, Fig. 4 shows the curves for the difference between drain current without SHE and with SHE (ΔID ), for the same VGT as a function of the power with SHE. The results show that, for the same power level, the ΔID is higher in FinFET devices i.e, the self-heating effect degrades the drain current much more than compared in JNT. Conclusions According to the results simulated, JNT suffer less self-heating effect when compared with a similar FinFET devices due to the decreasing of the mobility variation with temperature. acknoledgment The authors acknowledge CAPES, FAPESP and CNPq for the financial support. References D. Hisamoto et al., IEEE Transactions on Electron Devices, vol.47 , pp. 2320-2325, 2000. J. T. Park et al., IEEE Electron Device Letters, vol.22, pp. 405-406, 2001. J. P. Colinge et al., IEEE Electron Device Letters, vol.24, pp. 515-517, 2003. J. P. Colinge et al., Proceeding of IEEE International SOI Conference, pp. 1, 2009. C. W. Lee et al., Appl. Phys. Lett., vol. 94, no. 5, p. 053 511, Feb. 2009. J. P. Colinge et al., Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010. G. Mariniello et al., Symposium on Microelectronics Technology and Devices (SBMICRO) 2013 v.1 p1-4. A. Kranti et al., Solid-State Electronics, vol. 65-66, pp. 33-37, Dec. 2011. S. Zimin et al., Proc. ICSICT, 1998, pp. 572-574. Sentaurus Device User’s Manual, Synopsys, 2013. Figure 1

This paper evaluates the roles of the electric field (E) and the density of carries (n) in the drain conductance of Junctionless Nanowire Transistors (JNTs). The behavior of E and n presented by JNTs with the variation of the gate and the drain voltages has been compared to the one presented by Inversion Mode (IM) Trigate devices of similar dimensions. It has been shown that the lower drain output conductance exhibited by Junctionless transistors with respect to the IM ones is correlated not only to the differences in the mobility and its degradation but also to the electric field, the density of carries and the first order derivative of these variables with respect the drain voltage.