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Stacked horizontal Gate All Around Nanosheet transistors were recently proposed as a replacement of FinFET for the sub-7nm device nodes. In order to stack Nanosheet channels, a specific SiGe/Si superlattice epitaxy is employed, with SiGe being used as a sacrificial layer that will define the suspension thickness (Tsus) between the channels. In this paper, we will consider the optimization of SiGe/Si multilayer epitaxy for Nanosheet channel definition (Fig. 1). Stacks with different Ge compositions are physically characterized and studied. With strain characterization and x-ray diffraction measurements on (100) substrates, we will show that it is possible to form pseudomorphic defect-free SiGe/Si multilayers over a wide range of Ge concentrations in the sacrificial SiGe (Fig. 2 and 3). The uniformity obtained on blanket 300mm substrates will be presented (Fig. 4), with a discussion on the SiGe/Si interface abruptness. In the context of CMOS device integration, it is necessary to employ a low temperature STI process to mitigate the Ge inter-diffusion in the silicon channel and to avoid the possible generation of defects from plastic relaxation of SiGe. The SiGe and Ge-Si intermixed regions are removed with appropriate selective etch process in two Nanosheet specific modules: inner spacer formation in the extension regions (Fig. 5) and post channel release in the gate regions (Fig. 6), leaving only 5nm intrinsic silicon Nanosheets. We will report the etch rate and selectivity of our in-house vapor-phase channel release process performed at low temperature. This process enables us to remove SiGe versus Si with a great selectivity and a limited amount of silicon loss during channel release, before gate stack deposition around the stacked Nanosheets. From a device perspective, we will show that the optimization of the silicon thickness in the SiGe/Si superlattice plays an important role in the Nanosheet device performance and electrostatics (Fig. 7). Finally, with a good SiGe/Si multilayer uniformity control, a reduced thermal budget and after optimization of our in-house SiGe selective etch process, we will show the capability to form 5nm silicon Nanosheet channels with small within wafer variation, low device variability and good process control, compatible with the fabrication of very large scale integrated circuits for future CMOS device nodes. Acknowledgements: This work was performed by the Research Alliance Teams at various IBM Research Facilities. Figure 1

With transistor scaling in 7nm technology and beyond, sacrificial silicon materials etches (e.g. dummy poly silicon gate removal) are considered to be among the most challenging hurdle in FinFET process development. In this paper, we present a dry chemical etch technique for selective etching of single crystal, poly-crystal and amorphous silicon on various FinFET device process steps. It was demonstrated that this technique could completely remove poly silicon in vertically high aspect ratio (AR>5) FinFET gates with a large process window (over-etch budget ~200%) while achieving the lowest gate leakage current and best short channel FET yield. Proper surface preparation, queue time control and etch by-product removal strategies are discussed. The residue free etch and etch by-product sublimation mechanisms are also investigated by High Resolution Electron Microscopy (HREM) and Fourier Transform Infrared Spectroscopy (FTIR) surface analysis. This work was performed by the IBM Research at various IBM Research and Development Facilities.

In agreement with the ITRS roadmap, there have been several publications supporting the reduction in critical dimensions and the introduction of new materials to semiconductor processing (1,2,3). This paper highlights the observations and solutions to some of the critical material and process interactions encountered during the integration of the back end of line interconnect.

Low-pH titanium nitride (TiN) removal formulations utilizing oxidizers other than hydrogen peroxide (H2O2) have been developed with superior TiN selectivity toward W and the inter-level dielectric (ILD) films. One critical challenge is protecting the TiN barrier layer between the W and dielectric layer, which is often exposed during the TiN metal hard mask (MHM) removal step. This study focused on developing and optimizing formulations with TiN MHM etch rates ≥ 100 Å/min at temperatures ≤ 60oC, with compatibility toward W, ILD films, and the TiN liner. The galvanic corrosion was tailored to protect the TiN liner in the presence of W. A simple yet novel patterned wafer test vehicle was developed to facilitate this work, enabling the investigation of the chemical impact at the W/TiN liner interface.

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