22 results on '"Misra, Veena"'
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2. Towards the Fabrication of Ultra-Thin SOI on Si (001) using Epitaxial Oxide and Epitaxial Semiconductor Growth Processes
3. Materials and Processes for High k Gate Stacks: Results from the FEP Transition Center
4. Workfunction Tuning of Nickel Silicide by Varying Nickel and Silicon Composition
5. Feasibility of Dipole Based Work Function Tuning for Sub-1nm EOT Metal Gated High-K Stacks
6. On the Issue of Work Function Tuning of Nickel Silicide Gates
7. Properties of ErSi(2−x) Contacts Formed on Si(1−x)C(x) Epitaxial Layers
8. (Invited) Interface Investigation of ALD Dielectrics on III-N Substrates for RF, Mixed Signal and Power Applications
9. Impact of ALD Gate Dielectrics (SiO2, HfO2, and SiO2/HAH) on Device Electrical Characteristics and Reliability of AlGaN/GaN MOSHFET Devices
10. Application of AlGaN/GaN Heterostructures for Ultra-Low Power Nitrogen Dioxide Sensing
11. Atomic Layer Deposition of SnO2for Selective Room Temperature Low ppb Level O3Sensing
12. Implications of Lower Zero-Field Activation Energy of Dielectric in Al2O3/HfO2 Bi-Layer Dielectric RRAM Forming Process
13. Platinum Nanoparticles Grown by Atomic Layer Deposition for Charge Storage Memory Applications
14. Atomic Layer Deposition of Hafnium Dioxide on TiN and Self-Assembled Monolayer Molecular Film
15. Erbium Silicide Formation on Si[sub 1−x]C[sub x] Epitaxial Layers
16. Investigation of VT Shift Mechanism of High-K Dielectrics caused by Lanthanum Capping for NMOS and Tantalum Capping for PMOS Devices
17. Reliability and Stability Issues for Lanthanum Silicate as a High-K Dielectric
18. Electrical and Physical Analysis of MoTa Alloy for Gate Electrode Applications
19. High-Temperature Stability of Lanthanum Silicate Gate Dielectric MIS Devices with Ta and TaN Electrodes
20. Electrical Characteristics of HfO[sub 2] Dielectrics with Ru Metal Gate Electrodes
21. Thermal Stability of TaSi[sub x]N[sub y] Films Deposited by Reactive Sputtering on SiO[sub 2]
22. A Low‐Thermal‐Budget In Situ Doped Multilayer Silicon Epitaxy Process for MOSFET Channel Engineering
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