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Heteroepitaxial growth of Ge on Si has great interest for various optoelectronic applications such as Ge photodiodes(1). However 4.2% of lattice mismatch causes dislocation formation and island growth. High quality Ge(001) growth techniques are reported in ref.(2-4). Moreover, Ge(111) surface is also interesting because of higher carrier mobility(5). Furthermore, Ge(110) is preferred orientation of virtual substrates for epitaxial graphene growth(6). In the case of the Ge deposition on Si(111) and Si(110) substrates, it seems that the process conditions used for Ge growth on Si(001) are not suitable to realize high crystallinity and smooth surface (7). In this paper, we present a method of high quality and smooth Ge layer growth on Si(111) and Si(110), which is the same level as the Ge growth on Si(001). Epitaxial growth of Ge on Si(111) and Si(110) is carried out using a reduced pressure chemical vapor deposition system. After HF last clean, a wafer is baked at 1000°C and cooled down to 600°C in H2 and further to 300-550°C in N2 to form a hydrogen-free Si surface. Then a 100 nm thick Ge layer is deposited as a seed layer using GeH4 with N2 carrier gas. Afterward the wafer is heated up to 450-650°C in H2 and the main part of Ge is deposited using a H2-GeH4 gas mixture. For threading dislocation density (TDD) reduction, annealing at 800°C in H2 is performed for several times (cyclic annealing) by interrupting the Ge growth. Atomic-force microscopy (AFM) is used for surface roughness analysis. Scanning transmission electron microscopy (STEM) and X-ray diffraction (XRD) are used for structural characterization of the Ge layer. Secco defect etching combined with angle view scanning electron microscopy (SEM) or optical microscope is used for TDD evaluation. Figure 1(a,b) summarize the root mean square (RMS) roughness of Ge(111) and Ge(110) seed layers grown at 300-550°C before and after postannealing at 600-800°C. If the growth temperature is lower than 350°C for Ge(111) and 400°C for Ge(110), a significant increase of the surface roughness is observed after postannealing at 700°C and 800°C, respectively. For both crystal orientations, the lowest RMS roughness is observed by depositing at 450°C for as deposited and postannealed samples. The maintained RMS roughness even after postannealing at 800oC may be indicating good crystal quality even at as deposited condition. To confirm the influence of the growth temperature on the crystallinity, cross section TEM images of the Ge(111) and the Ge(110) seed layers deposited at 300°C and 450°C are shown in Fig. 2(a-d). In the case of Ge growth at 300°C (Fig. 2(a,b)), a very high density of stacking faults (SF) and high surface roughness are observed for both crystal orientations. In contrast, by depositing at 450°C (Fig. 2(c,d)), lower SF density in the Ge layer is observed compared to that at 300°C. By postannealing, an improvement of crystallinity is observed for the Ge seed layers deposited at 450°C. However, in the case of 300°C, the crystallinity cannot be improved by the postannealing, because a too high density of dislocations and SF may cause irregular Ge atom migration. As the result, surface roughening occurs. Figure 3(a,b) show AFM surface roughness images after 5 μm-thick Ge(111) and Ge(110) deposited with cyclic annealing at 800°C, respectively. Clear terraces of ~0.3 and ~0.2 nm, whose heights are close to those of Ge(111) bilayer and Ge(110) monolayer, are observed, respectively. RMS roughness of the Ge(111) and the Ge(110) are 0.51 and 0.35 nm, respectively. These RMS roughnesses are comparable to a level reported for Ge (001) in ref.(1). Figure 4 shows TDD of Ge(111) and Ge(110) surfaces as a function of the Ge thickness deposited with cyclic annealing on Si(111) and Si(110) substrates. For both orientations, TDD of ~4×108 cm-2 is obtained for 500 nm-thick samples. With increasing the Ge thickness, the TDD is reduced and levels below TDD of ~5×106 cm-2 are achieved for both Ge (111) and Ge(110) for 5 μm-thick Ge. These methods enable high quality virtual substrate fabrication not only for (001) surfaces but also for (111) and (110) orientation without a chemical mechanical polishing process. References Lischke et al. Nature Photonics15 (2021) 925 Yamamoto et al. Solid-State Electron. 60 (2010) 2 Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007 M. Hartmann et al. J. Appl. Phys. 95 (2004) 5905 H. Lee et al. IEDM Tech. Digest (2009) 09-457 J-H. Lee et al. Science 344 6181(2014) 286 M. Hartmann et al. J. Cryst. Growth 310 (2008) 5287 Figure 1

Multilayered Ge nanodots have drawn much attention due to their potential applications in optoelectronics, such as photodetectors and lasers. Many groups studied multilayered Ge nanodots with Si spacers on Si(001) grown by Stranski-Krastanov (SK) growth mode and vertically aligned by local tensile strain induced by buried Ge nanodots (1-2). However, to avoid plastic relaxation caused by a 4.2% lattice mismatch between Si and Ge, thick nanodots and/or large layer numbers are challenging. Additionally, laterally-aligned Ge nanodots without pre-structuring have not been reported. In this study, we demonstrate 3-dimensional (3D) self-ordered Ge nanodots on SiGe virtual substrate (VS) by SiGe/Ge cyclic epitaxial growth and show the effects of fabrication parameters. The 3D self-ordered Ge nanodots were fabricated by reduced-pressure chemical vapor deposition. A Si0.4Ge0.6 VS with step-graded buffer deposited on Si(001) wafer was used. This VS was post-annealed at 1000°C, followed by chemical-mechanical polishing. After HF dip, the substrate was baked at 850°C in H2, then cooled down to 550°C for epitaxial growth. A 52-82 nm thick Si0.48Ge0.52 layer was deposited using a H2-SiH4-GeH4 gas mixture, then a self-assembled Ge nanodots layer via SK growth mechanism was deposited with 7.5-15.0 nm Ge coverage using a H2-GeH4 gas mixture. This Si0.48Ge0.52/Ge deposition cycle was repeated 5 to 20 times to fabricate the 3D self-ordered Ge nanodot stack. Atomic force microscopy (AFM) and scanning electron microscopy (SEM) were used to analyze the morphology and alignment of the Ge nanodots. The facets of the Ge nanodots were studied by analyzing the cross-section cuts of AFM images and confirmed by scanning transmission electron microscopy (STEM). Nano-beam diffraction (NBD) was used to study strain in the superlattice. Fig. 1(a-c) show the AFM images of the 5-cycle superlattices with Ge coverage 7.5 to 15.0 nm. In fig. 1(a), we can see mainly two types of nanodots, diamond (32%) and dome (68%). The height of the diamond-like nanodots is 9 nm with a standard deviation (s) of 2.6 nm while that of the dome-like nanodots is 23 nm with s=1.8 nm. With increasing Ge coverage, dome-like nanodots dominate (fig. 1(b)) and some nanodots merge with the adjacent nanodots (fig. 1(c)). Since the dome-like nanodots show a lower s in height than the diamond-like nanodots do, engineering of self-ordering is more feasible with the dome-like nanodot. Fig. 2(a-b) show the angle view of SEM images of Ge nanodots on 5- and 20-cycle superlattice of 12.5 nm-Ge/52 nm-SiGe. The dome-like nanodots are dominant and laterally aligned. The alignment and the uniformity improve with the increasing cycle number of the superlattice. However, when the thickness of Si0.48Ge0.52 spacer increases, the lateral- and vertical alignment of nanodots become random, and the amount of diamond-like nanodots increases (not shown). To study facets of two types of nanodots, the tilt of each facet was calculated from the cross-section cuts of AFM images. Fig. 3(a) shows an AFM image of the dome-like nanodot. Fig. 3(b) shows the cross-section cuts of fig. 3(a) along . These cross-section cuts are well-overlapped with the high-angle annular dark-field (HAADF) STEM image as shown in the background of fig. 3(b). Therefore, it is possible and reliable to estimate the facets from the cross-section cuts of our AFM images. By this method, we confirmed that the diamond-like nanodot is composed of {105} and the dome-like nanodot is composed of {113} and {159}. This is consistent with a study of Ge dot on Si substrate except for {159} facet (3). Instead of {159} facet, a relatively similar facet {3 15 23} was reported. This difference may result from the less compressive strain in our Ge nanodots because SiGe VS was used. To explain the vertical correlation of Ge nanodots, a HAADF STEM image and in- and out-of-plane strain distributions measured by NBD are shown in fig. 4(a-c). The nanodots are vertically aligned (fig. 4(a)). The SiGe on the nanodot shows a relatively higher lattice parameter along (fig. 4(b)) and lower lattice parameter along (fig. 4(c)) compared to that on Ge wetting layer, indicating tensile strain. This tensile strain area is the preferred position for Ge nanodot formation because of less lateral lattice mismatch. Consequently, the nanodots tend to grow above the buried nanodots. 3D self-ordered multilayered Ge nanodots on SiGe VS were successfully fabricated, and the facets and the vertical correlation of Ge nanodots were studied. References P.S. Chen et al. Materials Science and Engineering B 108 (2004) 213-218 K.L. Wang et al. Proceeding of the IEEE 95 (2007) 1866 J.T. Robinson et al. Nanotechnology 20 (2009) 085708 Figure 1

Dislocation free local SiGe-on-insulator virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around ~1.25 µm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO2 / Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO2 cap, is obtained. Uniform Ge content of ~40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ~0.65% is found which could be due to thermal expansion difference between SiO2 and Si. In the SiGe, tensile strain of ~1.4% along direction, which is higher compared to that along direction, is observed. The tensile strain is induced from both [110] and [-110] directions. Threading dislocations in the SiGe are located only ~400 nm from Si pillar and stacking faults are running towards directions, resulting in wide dislocation-free area formation in SiGe along due to horizontal aspect ratio trapping.

Three-dimensional (3D) self-ordered Ge nanodots in cyclic epitaxial growth of Ge/SiGe superlattice on Si0.4Ge0.6 virtual substrate (VS) were fabricated by reduced pressure chemical vapor deposition. The Ge nanodots were formed by Stranski-Krastanov mechanism. By the Ge/SiGe superlattice deposition, dot-on-dot alignment and 〈100〉 alignment were obtained toward the vertical and lateral direction, respectively. Facets and growth mechanism of Ge nanodots and key factors of alignment were studied. Two types of Ge nanodots were observed, diamond-like nanodots composed of {105} and dome-like nanodots composed of {113} and {519} or {15 3 23} facets. The Ge nanodots tend to grow directly above the nanodots of the previous period as these regions show a relatively higher tensile strain induced by the buried nanodots. Thus, this dot-on-dot alignment is sensitive to the SiGe spacer thickness, and it degrades when the SiGe spacer becomes thicker. The Ge content of the SiGe spacer ranging from 45 to 52% affects the lateral alignment and the size uniformity of Ge nanodots because of the strain balance between the superlattice and the VS. By maintaining the strain balance, ordering of the 3D aligned Ge nanodots can be improved.

A method for high quality epitaxial growth of Ge on Si (111) and Si (110) is investigated by reduced pressure chemical vapor deposition. Two step Ge epitaxy (low temperature Ge seed and high temperature main Ge growth) with several cycles of annealing by interrupting the Ge growth (cyclic annealing) is performed. In the case of Ge seed layer growth below 350 °C for (111) and 400 °C for (110) orientation, huge surface roughening due to too high dislocation density is observed after the following annealing step. For both crystal orientations, a high crystallinity Ge seed layer is realized by combination of 450 °C growth with 800 °C annealing. Once the high-quality Ge seed layer is deposited, high crystal quality Ge can be grown at 600 °C on the seed layer for both crystal orientations. For the 5 μm thick Ge layer deposited with the cyclic annealing process at 800 °C, a Si diffusion length of ∼400 nm from the interface, RMS roughness below 0.5 nm and threading dislocation density of 5 × 106 cm−2 are achieved for both (111) and (110) substrates.

SiGe virtual substrates (VS) having low-surface roughness with less defects are essential for fabricating emerging quantum devices such as qubits. Various techniques to grow VS are reported e.g. conventional graded buffers (1,2) and reverse graded buffers (3). However, these methods require several micrometer-thick buffer layers, having threading dislocations (TDs) network and develop crosshatch patterns resulting in high surface roughness, needing chemical mechanical polishing for planarization. In our previous work, lateral-selective Ge growth (4) was performed in a cavity formed by selective vapor phase etching (VPE) of Si from side of mesa-patterned SiO2 /Si structures fabricated on buried oxide (BOX) to create smooth and dislocation-free local Ge by horizontal aspect ratio trapping (ART). In this work, we demonstrate lateral-selective SiGe growth to realize smooth and dislocation-free local SiGe VS by lateral ART and discuss its surface morphology, strain and dislocations. Lateral-selective SiGe growth is done in a reduced-pressure chemical vapor deposition (RPCVD) system. Thermally oxidized silicon-on-insulator (SOI) wafers with 300 nm SiO2/300 nm Si/2 μm BOX are used. For the sample preparation, 6.3 μm square checkerboard SiO2/Si mesa structure with [110] oriented sidewalls is fabricated by photolithography patterning and reactive ion etching. After standard RCA cleaning followed by HF dip, the wafer is loaded into RPCVD reactor and pre-baked at 850oC in H2 to remove residual oxide. Thereafter, lateral HCl VPE of Si is performed at 850oC from side of mesa. Si pillar remains at center of the mesa. Then, SiGe is selectively deposited in the cavity around the Si pillar using a SiH2Cl2-GeH4-HCl gas mixture at 750oC. Finally, the top SiO2 is removed by HF. Atomic force microscopy (AFM) is used to measure the surface roughness. Energy dispersive X-Ray spectroscopy (EDX) is used for measuring Ge content distribution in SiGe. Micro-Raman spectroscopy is used to analyze strain distribution in Si and SiGe. Nano-beam diffraction (NBD) is employed for estimating the relative change of in- and out-of-plane SiGe lattice parameters. Plan-view transmission electron microscopy (TEM) is used for imaging dislocations. Fig. 1 shows the AFM image for surface morphology of lateral-selective Si0.6Ge0.4 around the Si pillar. SiGe has root mean square roughness of ~0.16 nm, which is similar to blanket Si(001) (~0.14 nm), because the SiGe surface roughness is determined by interface roughness of top SiO2 and sacrificially etched Si. Uniform Ge content of ~40% in SiGe layer is observed by EDX analysis (Fig. 2). In the Si pillar part of Fig. 3, relative uniform tensile-strain of ~0.4% is observed. Since Si is negligibly strained in unpatterned area of SOI (taken as reference), hence during HCl VPE at 850oC, Si pillar/SiO2 interface could slip by higher thermal expansion of Si as interface decreases. Tensile-strain in Si pillar could be formed during cooling process. Ideally, ~1.68% lattice mismatch strain should exist in fully-relaxed ~40% SiGe on Si. However, higher tensile-strain (~2.5%) in SiGe is observed at corners along [010]. To clarify the reason of higher strain at corners, in- and out-of-plane SiGe lattice parameters near Si pillar (as marked in Fig 4(a)) are investigated by NBD. Higher in-plane lattice parameter in [110] is observed in the edge part of the SiGe lamella as compared to the center part (Fig. 4(b)). However, out-of-plane lattice parameter in [001] is homogeneous across entire SiGe (Fig. 4(c)). Because SiGe has uniform Ge concentration as shown in Fig. 2, higher lattice parameter in the edge part of Fig. 4(b) is caused by strain difference. This is because SiGe lamella edge (away from Si pillar) is more relaxed as compared to SiGe lamella center (beside Si pillar) which is confirmed by vertically grown ~700 nm 40% SiGe on blanket Si(110). Symmetric strain distribution does also exist in 90° rotated direction. Therefore, the tensile-strain in [010] is induced from both [110] and [-110]. In Fig. 5, stacking faults of SiGe on (111) plane are observed along [110] and [1-10]. TDs are present along [111], terminated by top SiO2/BOX and located up to first ~400 nm from Si while misfit dislocations are at Si/SiGe interface. Wide dislocation-free area in SiGe is present along [010]. This technique enables dislocation-free local SiGe-on-insulator substrate fabrication which can be applied for thin and high quality VS for the quantum devices. References E. A. Fitzgerald et al., J. Appl. Phys., 63, 693 (1988). E. A. Fitzgerald et al., Appl. Phys. Lett., 59, 811 (1991). V. A. Shah et al., Appl. Phys. Lett., 93, 192103 (2008). Y. Yamamoto et al., ECS J. of Solid State Sci. and Technol., 3, 353 (2014). Figure 1

The influence of introducing a SiGe/Ge superlattice (SL) between Ge layers and Si substrate for the sake of the reduction of the threading dislocation density (TDD) without additional annealing is investigated. By introducing the SiGe/Ge SL and optimizing the layer stack, the TDD of the Ge layer becomes ∼1/3. In the case of 2.8 μm thick Ge without introducing the SiGe/Ge SL, the TDD at the surface is 7.6 × 108 cm−2. A slight TDD reduction is observed by introducing a Si0.2Ge0.8/Ge SL between the Si substrate and the Ge layer. By inserting 5, 10 and 20 cycles of Si0.2Ge0.8/Ge, the TDD is reduced to 7.1 × 108, 5.9 × 108 and 5.3 × 108 cm−2, respectively. The lateral lattice parameters of these SLs are ∼5.656 Å, which is a smaller value compared to that of bulk Ge, indicating plastic relaxation by misfit dislocation formation. Further TDD reduction is realized with increasing Si concentration in the SiGe/Ge SL without changing the cycle of the SL. However, surface roughening due to pit formation occurs if the Si concentration in the SL is higher than 50% because of increased strain at the interfaces between SiGe and Ge. With increasing SiGe and Ge thickness ratio in the SL layer and maintaining periodicity and cycles, the TDD is reduced to 2.8 × 108 cm−2 without degrading the surface roughness. This improvement is related to a relaxation of the SiGe/Ge SL by plastic deformation.

Ge growth on Si is essential e.g. for photonics device integration (e.g. Ge photodiode) into Si based CMOS platform (1). However, due to 4.2% of lattice mismatch between Ge and Si, misfit dislocations (MD) and threading dislocations (TD) are introduced for strain relaxation after exceeding critical thickness. In order to realize low-darkcurrent Ge photodiode, improvement of crystallinity is important. High quality Ge growth techniques by combining various annealing techniques (at 800~850oC) are reported (2-3). However, because of low melting point of Ge (937oC), the Ge growth process is typically integrated at the last part of front-end process. Therefore, these annealing processes are affecting device parameters of existing devices. In previous paper, we reported Ge/SiGe superlattice (SL) fabrication and found improvement of TD density (TDD) by increasing Si composition of SiGe in the SL (4). Here we report TDD improvement of Ge by introducing the SL without annealing. Ge growth with SiGe/Ge SL is carried out using reduced pressure chemical vapor deposition system. Si(100) wafers are used. After an HF last cleaning, the wafer is loaded into reactor and baked at 1000oC and cooled down to 600oC in H2 and further cooled down to 350oC in N2. After that 100 nm-thick seed Ge is deposited using N2-GeH4 gas. Then the wafer is heated up to 500oC in H2 and Ge/SiGe superlattice is fabricated using H2-GeH4 and H2-SiH4-GeH4 gases, respectively. Furthermore, 2.8 µm thick Ge is deposited at 550oC using H2-GeH4 gas. Thickness is measured by cross section SEM and spectroscopic ellipsometry. TDD is determined by Secco defect etching technique. Strain and relaxation of Ge and SiGe layers are measured by XRD reciprocal space mapping. Distribution of the MD and the TD are measured by cross section TEM. In the case of direct Ge growth on Si (Fig. 1a), MDs are formed at interface between Ge and Si. TDs are spreading into the Ge layer. Some of the TDs are long and extending to surface. These MD and TD formations are due to the lattice mismatch between Ge and Si. On the other hand, in the case of Ge sample grown on ×20 Si0.3Ge0.7 / Ge SL (Fig. 1b), most of MDs are formed at interface between 100 nm-thick Ge buffer and Si substrate. Additionally high density of TDs are observed in the Ge buffer and the SL layer. In the SL layer, lower TDD is observed in the upper part compared to that in the deeper part. At the interface between upper 2.8 µm thick Ge and the SL layer, MD and high density of TDs toward lateral direction is observed indicating relaxation. TDD in the 2.8 µm thick Ge layer seems to be lower compared to that in Fig. 1a). In the case of direct Ge growth on Si, TDD of ~7.5×108 cm-2 is obtained (Fig. 2). The TDD is comparable to previously reported results (2). By depositing 2.8 µm thick Ge on Si0.2Ge0.8 SL, TDD is decreased to ~5.4×108 cm-2. With decreasing Ge concentration of SiGe layer of the SL, decrease of TDD is observed until 40%. However, by replacing SiGe layers to mono-layers of Si, increased TDD is observed, which might be due to too high strain at interface between Si and SiGe. Figure 3 shows TDD of 2.8 µm thick Ge deposited on Si0.2Ge0.8/Ge SL with different Si0.2Ge0.8 and Ge thickness combination without changing periodicity of the SL. Lower TDD is observed when the 2.8 µm thick Ge is deposited on the SL with higher Si0.2Ge0.8 thickness. Possible reason is higher degree of relaxation of the SL layer. In Fig. 4, TDD of 2.8 µm thick Ge deposited on SLs of various lattice parameters are shown. By reducing lateral lattice parameter of the SiGe/Ge SL by increasing SiGe thickness or Si concentration, TDD decreases. The reduction of the TDD is fitting to one line for both cases. These results indicate that higher plastic relaxation of the SL occurs on the Ge buffer due to increased compressive strain of SiGe in the SL, and the TDD reduction of the Ge on the SL may be caused by similar mechanism of reverse graded buffer. By introducing SiGe/Ge SL, multiple effect of the reverse graded buffer may be expected. Reference (1) S. Lischke et al. Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) , (2014) 29 (2) Y. Yamamoto et al Solid-State Electron. 60 (2011) 2 (3) Y. Yamamoto et al. Semicond. Sci. Technol. 33 (2018) 124007 (4) Y. Yamamoto et al. Jpn. J. Appl. Phys. 59, SGGK10 (2020) Figure 1

The oxygen precipitates formed in Czochralski (CZ) silicon wafers in consequence of the thermal treatment were investigated since many decades. The main reason why so much effort was directed towards these defects was the impact which they have on integrated circuits and properties of silicon wafer itself. Oxygen precipitates can increase the resistivity of CZ silicon, change the wafer strength and cause warpage of the wafers. It was also demonstrated that metal impurities can be effectively trapped at oxygen precipitates in the process of gettering, what is a huge advantage. All these features of the oxygen precipitates require the control of precipitation in the production process of silicon devices. However, this cannot be optimally executed if the features of oxygen precipitates like their composition are not fully known. In spite of the wide knowledge of oxygen precipitation, the composition of oxygen precipitates SiO x still remains under ongoing discussion. This is due to the different x values varying from x=1 to x=2 which can be found in the literature. In this work, we look on the current stage of the investigation on the composition of oxygen precipitates obtained with the help of different techniques. Moreover, we present our recent investigation on the composition of oxygen precipitates carried out by means of energy dispersive X-ray spectroscopy (EDX), electron energy loss spectroscopy (EELS) and Fourier transform infrared spectroscopy (FTIR). The FTIR spectra measured at liquid helium temperature will be compared with the spectra simulated on the basis of experimental results obtained by scanning transmission electron microscopy (STEM). The EDX gives direct information about the composition of oxygen precipitates. However, the analysis of the EDX spectrum requires a special calibration. This is due to the limitation of EDX for light elements like oxygen. The intensity of characteristic X-rays of oxygen depends on the thickness of TEM lamellae. Therefore, in this work we measured a thermally grown SiO2 layer at different thickness of TEM lamellae in order to determine the influence of the lamellae thickness on the intensity of oxygen characteristic X-rays. After doing this, we measured the composition of oxygen precipitates located at very thin TEM lamellae. The results shown that x is in the range between 1.8 and 1.9 (1). To make sure that the EDX results are correct EELS measurements were carried out. EELS is a complementary method to EDX. It allows to avoid the limitation of EDX in the measurement of the composition of oxygen precipitate especially in the case if the precipitate does not go through the TEM lamellae. Deconvoluting the characteristic plasmons of Si, SiO2 and suboxides in the electron energy loss spectra we found that the oxygen precipitate consist of SiO2 and it is coated by thin 2-3nm SiO layer (2). Finally, we investigated the composition of oxygen precipitates by FTIR. The absorption band of oxygen precipitates were observed in FTIR spectra measured at liquid helium temperature. The position and the shape of the bands fit very well to the simulated spectra. The simulation of the spectra was conducted on the basis of the effective medium theory (EMT) where we considered SiO2 spheroids coated by SiO layers embedded in a Si matrix. In summary, the composition of oxygen precipitates was investigated by EDX, EELS and FTIR whereby the first two methods are direct methods and the latter one is an indirect method. All methods delivered similar results. Hence, we can conclude that the oxygen precipitates consist of a SiO2 core which is coated by an SiO layer. References 1D. Kot, G. Kissinger, M. A. Schubert, M. Klingsporn, A. Huber, and A. Sattler, Phys. Status Solidi RRL 9, 405 (2015). 2G. Kissinger, D. Kot, M. Klingsporn, M.A. Schubert, A. Sattler, T. Müller, ECS J. Solid State Sci. Technol. 4 (9), N124-N129 (2015).

In a previous work, we found that both the interface between an oxide precipitate and the surrounding silicon matrix and the interface between a silicon substrate and a thermal oxide layer are of the same nature [1]. In both cases, between SiO2 existing in the center of the precipitate and in the oxide layer and Si of the matrix and the substrate a suboxide region of 2-3 nm exists. These results were obtained by electron energy loss spectrometry (EELS) carried out by scanning transmission electron microscopy (STEM). In the low loss region, it is possible to distinguish between Si, SiO, and SiO2 which all exhibit different maxima of the plasmon loss energy. By deconvolution, the local composition of the phase can be determined with the help of reference spectra of the three components. The stoichiometry of the oxide precipitates (SiO x ) was debated for a long time and application of different methods on different samples containing oxygen precipitates resulted in different values for x ranging from 1 to 2. Recently, it was demonstrated by applying several direct and indirect methods that the oxide precipitates consist of SiO2 [2]. Inspired by the results in Ref. 1 and 2, a layer model was proposed explaining the different values for x for oxide precipitates of different geometry [3]. Especially, for plate-like precipitates with a large surface the lower x values could be explained. Now the question came up if the width of the interface between Si and SiO2 is constant for all growth temperatures because from interface physics it could be expected that its width increases with temperature. Another point is, if the thickness of oxide layer or oxide precipitates plays a role. For this reason, we again used thermal oxide layers on (100) silicon of different thickness grown at different temperature to investigate the composition profile across the interface. We also compared the results with profiles from plate-like oxide precipitates grown at different temperatures. A scanning transmission electron microscope (STEM) FEI Tecnai Osiris equipped with tools for energy dispersive X-ray spectroscopy (EDX) analysis and EELS was used to analyze the interface and composition of a plate-like precipitates located at a very thin place of the lamella prepared from the sample by grinding, polishing, and ion milling. The profiles of the x values across the interfaces of the oxide layers and the precipitates were determined from the deconvolution of the Si, SiO, and SiO2 EELS spectra. The results of these investigations demonstrate that the stoichiometry of SiO2 (x=2) cannot be reached if the oxide layer thickness is lower than 10 nm for thermal oxides grown at 900 °C. The lower the thickness of the layer is the lower is the maximum x value. This is due to an interface layer of equal maximum slope for all oxide layers. The slope was obtained from fitting by sigmoid functions. Such interface layers were also found for the oxide precipitates but the maximum slope is lower. It was found to increase with increasing diffusion length of interstitial oxygen. The maximum of the x profiles also depends on the thickness of the plate-like oxide precipitates. The results will be discussed with respect to the phase separation process leading to precipitation of interstitial oxygen in silicon. References [1] G. Kissinger, D. Kot, M. Klingsporn, M.A. Schubert, A. Sattler, T. Müller, ECS J. Solid State Sci. Technol. 4 (9), N124-N129 (2015). [2] D. Kot, G. Kissinger, M. A. Schubert, M. Klingsporn, A. Huber, and A. Sattler, Phys. Status Solidi RRL 9, 405 (2015). [3] J. Vanhellemont, Phys. Status Solidi RRL 9, 597 (2015).

One of the reasons why the principal gettering mechanism of copper at oxide precipitates is not yet clarified is that it was not possible to identify the presence and measure the copper concentration in the vicinity of oxide precipitates. To overcome the problem we used a 14.5 nm thick thermal oxide layer as a model system for an oxide precipitate to localize the place where the copper is collected. We also analyzed a plate-like oxide precipitate by EDX and EELS and compared the results with the analysis carried out on the oxide layer. It is demonstrated that both the interface between the oxide precipitate being SiO2 and the silicon matrix and the interface between the thermal oxide and silicon consist of a 2–3 nm thick SiO layer. As the results of these experiments also show that copper segregates at the SiO interface layer of the thermal oxide it is concluded that gettering of copper by oxide precipitates is based on segregation of copper to the SiO interface layer. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0151509jss] All rights reserved.

Dislocation generation and propagation during flash lamp annealing for 20 ms was investigated using wafers with sawed, ground, and etched surfaces. Due to the thermal stress resulting from the temperature profiles generated by the flash pre-existing dislocations propagate into the wafer from both surfaces during flash lamp annealing. A dislocation free zone was observed around 700 μm depth below the surface of a 900 μm thick sawed wafer. The dislocation propagation can be well described by a three-dimensional mechanical model. It was further demonstrated that in wafers being initially free of dislocations no dislocations are generated during flash lamp annealing. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0151507jss] All rights reserved.

High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. By plan view TEM, it is shown that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] and [1–10] direction resulting Ge grown toward [010] direction contains no dislocations. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. A root mean square of roughness of ∼0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2. © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0071411jss] All rights reserved.

Technologies of group IV semiconductor fabrication enable new artificial materials such as superlattice and nanodot structures (1). In particular, three dimensional (3D) ordered SiGe or Ge structures are promising materials to improve quantum dot lasers that can be integrated into existing CMOS platforms (2). In order to control regularly ordered nucleation sites, usually pre-patterning of the substrate is required. In the case of 3D stacking of Ge nanodots on Si substrates, the Ge nanodots tend to grow vertically aligned, due to the elastic strain field of the buried Ge nanodots (3). In a previous study, we reported a self-ordered body-centered tetragonal (BCT) SiGe nanodot formation using reduced pressure (RP) CVD, by repeating SiGe and Si layer stack deposition (4). By repeating several cycles of the SiGe and Si layer stack deposition, checkerboard Si mesas are formed on embedded SiGe dots and next SiGe dots are formed in concave region between the Si mesas. In this study we discuss the influence of Si surface roughness on the Ge nanodot formation and present a self-ordered 3D Ge nanodot formation. 3D Ge nanodot layer stack fabrication is carried out by using a single wafer RPCVD system. Standard Si (100) wafers are used. After H2 bake in the reactor, GeH4 is injected at 550°C to form Ge nanodots. Then a Si cap is deposited using H2-SiH4 at 600°C followed by H2-SiH2Cl2 at 700°C. In order to investigate the influence of surface roughness and strain on the Ge nanodot formation, a checkerboard Si mesa with ~7 nm height is fabricated by BCT Si0.6Ge0.4 nanodot layer stacks (4) for selected samples. Surface morphology is measured by AFM and SEM. Alignment of the Ge nanodots is measured by cross section SEM and TEM. Periodicity is measured by X-ray diffraction. By GeH4 exposure at 550°C Ge nanodots (Diameter: ~50, height: 2 nm) with ~6×1010 cm-2 were randomly formed on the Si surface. By postannealing at 600°C, migration of the Ge nanodots occurs resulting in larger Ge nanodots (Diameter: ~60 nm, height: 5 nm) and lower density (~1.5×1010 cm-2) as shown in Fig. 1. On the other hand, in the case of the checkerboard mesa structured Si surface fabricated by BCT Si0.6Ge0.4 nanodot underneath (RMS: 1.2 nm) (Fig. 2a), Ge nanodots are formed in concave region (Fig. 2b). This phenomenon is also observed for SiGe nanodot (4). The position of the Ge nanodot formation seems to be determined by a balance of strain field over embedded SiGe dots and surface energy. In this case, surface energy reduction seems to be more dominant compared to strain at the Si surface transferred from embedded Si0.6Ge0.4. In Fig 3, a cross section STEM image of 6 layers of Ge nanodot with Si spacer layer stack on the staggered aligned SiGe nanodot is shown. The Ge nanodots are vertically aligned. As shown in Fig. 2b, the first Ge nanodots are formed in the concave regions of the Si surface, therefore the first Ge nanodots are aligned to embedded SiGe nanodots underneath. By depositing a Si cap layer on the first Ge nanodots, a smoother Si surface (RMS: 0.5 nm) is formed compared to the initial checkerboard structure. By following GeH4 exposure, a second Ge nanodot formation occurred on the embedded Si surface. The aligned Ge nanodot formation seems to be driven by the tensile strain field at the Si surface above embedded Ge nanodots, because of a smooth Si surface. In Fig. 4a and 4b, nano beam diffraction (NBD) images of out-of-plane and in-plane strain distribution of the vertically aligned Ge nanodot structure are shown, respectively. The positions of the Ge nanodots are visible by higher vertical lattice parameter (Fig. 4a). In the Si part, smaller vertical lattice parameters are observed above the Ge nanodots compared to other area, indicating that the Si on the Ge nanodot is tensile strained. In the lateral lattice parameter distribution (Fig. 4b), only a periodic strain variation is visible, but to identify the position of the Ge nanodot is not possible, indicating that the 3D Ge nanodot stack is pseudomorphically grown. These NBD results support the assumption of Ge nanodot alignment discussed in Fig. 3. In this study we demonstrated self-ordered and vertically aligned Ge nanodot layer stack fabrication. Reference (1) K. L. Wang et al., Mat. Sci. in Semicond. Proc. 8 (2005) 389 (2) G. Capellini et al., Appl. Phys. Lett. 82 (2003) 1772 (3) Y. Nakaumura et al., Nanotechnology 21 (2010) 095305 (4) Y. Yamamoto et al., Nanotechnology 28 (2017) 485303 Figure 1

Silicon (Si)-based group IV materials form the backbone of our digital society, being found in every smartphone and tablet. They, however, lack the possibility to efficiently emit and detect light, because of their indirect bandgap. A truly Si-compatible direct bandgap material allows merging of state-of-the-art CMOS technology on-chip with photonic components to tackle bottlenecks of modern electronics by radically reducing the required power consumption or increasing the available data bandwidth [1]. Alloying the group IV elements germanium (Ge) and tin (Sn) has turned out to be a viable solution, as a direct bandgap semiconductor – even suitable for lasing – is formed for relaxed epilayers with Sn incorporation above ∼9 at.% [2]. The value of the bandgap can further be controlled by adding Si into GeSn, which can be exploited for carrier confinement inside heterostructures [3]. In this contribution, we discuss the epitaxy of various Sn-based group IV alloys. Different heterostructure designs combine direct bandgap active layers, ternary barriers and a GeSn buffer technology. In Figure 1a, a TEM micrograph of a SiGeSn/GeSn/SiGeSn double heterostructure (DHS) is presented, overlapped with the elemental distribution taken by energy-dispersive X-Ray spectroscopy (EDX). A Sn incorporation of roughly 14.5 at.% ensures a direct bandgap inside the active region. Another approach facilitates direct bandgap GeSn multi quantum wells (MQW), sandwiched between SiGeSn barriers. Atom Probe Tomography (APT) allows to obtain precise elemental distribution within this complex heterostructure stack, as is demonstrated in Figure 1b. Techniques such as temperature-dependent photoluminescence are used to compare the optical properties of the grown heterostructures. Moreover, the impact of quantum confinement on MQW emission is revealed, backed up by bandstructure calculations. Optically pumped microdisk resonators are formed to demonstrate lasing from different types of heterostructures, as shown in Figure 1c. As depicted in the inset, the superiority of MQW structures over DHSs (and bulk GeSn layers) is demonstrated, leading to an order of magnitude reduced lasing thresholds at cryogenic temperatures. In the next step of integrated light emitters, carriers need to be injected electrically, rather than optically. We will show first experiments on epitaxially grown p-i-n heterostructure diodes. In Figure 1d, incorporation of phosphorus and boron for the formation of n- and p-doped carrier injection layers is shown by SIMS. We will further point towards possible improvements that may pave the way towards future energy efficient opto-electronic integrated circuits (OEICs). [1] L. Vivien, Computer technology: Silicon chips lighten up, Nature. 528 (2015) 483–484. [2] S. Wirths, R. Geiger et al., Lasing in direct-bandgap GeSn alloy grown on Si, Nat. Photonics. 9 (2015) 88–92. [3] N. von den Driesch et al., Advanced GeSn/SiGeSn Group IV Heterostructure Lasers, Adv. Sci. (2018). doi:10.1002/advs.201700955. Figure 1

With the introduction of the Czochralski method for growing of silicon single crystals oxygen in silicon became an issue with positive and negative impact on silicon devices. On the one hand the oxygen strengthens the wafers against slip dislocation formation, on the other hand precipitating oxygen in the device active area can degrade the device performance. However, oxygen precipitates in the bulk are beneficial because they act as gettering sinks for metallic impurities and thus can improve the device performance. Therefore, oxygen is a major issue in silicon defect engineering. Extensive research on oxygen precipitation started in the seventies of the 20th century and it is still ongoing because new tools become available which offer new possibilities of characterization, higher resolution and lower detection limits. In the field of modeling, the tremendous advances of computer technique and software during the last decades made it possible for a much broader community to run larger models and to make predictions being much more sophisticated. The challenges of defect engineering in silicon device technology changed over the years. In the eighties, two or three step heat treatments were applied to out-diffuse the interstitial oxygen from the device active area followed by nucleation and growth of oxygen precipitates. This procedure is very time consuming. In the nineties, a new RTA based method was discovered. Vacancy profiles, which controlled the spatial distribution of oxygen precipitation in the wafers, were generated by high temperature RTA treatment. During this method, the oxygen does not diffuse out. Because intrinsic point defects are very fast diffusors, a good adjustment to the following device process has to be made. Today, one of the major requirements of high end silicon device technology is void-free silicon because with ongoing decreasing feature size voids became a major yield decreasing problem. There are several solutions to this issue like the growth of void-free silicon crystals and void dissolution in silicon wafers by heat treatment at very high temperature. Both methods are strongly connected with oxygen precipitation. Growth of nearly void-free silicon often leads to radial inhomogeneities of the concentrations of intrinsic point defects [1, 2]. The challenge of defect engineering is to create a radially homogeneous concentration of oxygen precipitates. The ongoing increase of wafer diameter imposes additional problems to oxygen precipitation. If the density of oxide precipitates becomes too high, overlay problems in mask alignment occur [3]. This requires new adjustments of oxygen precipitation. The low feature size in addition to the large wafer diameter asks for low thermal budget processing. A new problem arises because the oxygen precipitates need a certain surface and density to be able to getter enough metallic impurities. Examples from our own recently published results about ab initio calculation for understanding of the initial stages of oxygen precipitation [4], EELS investigation of the stoichiometry of oxygen precipitates [5], the gettering mechanism of Cu at oxygen precipitates [6], and N-doping for the homogeneous oxygen precipitation during high temperature annealing in wafers optimized with respect to voids [1, 2] will be presented. In summary, it can be said that oxygen in silicon remains an ongoing issue. Control of oxygen precipitation becomes more and more demanding for high end device technologies. Oxygen precipitation is not yet fully understood but the current developments of diagnostic methods allow new insights. [1] G. Kissinger, G. Raming, R. Wahlich, T. Müller, 300 mm Czochralski silicon wafers optimized with respect to voids with laterally homogeneous oxygen precipitation, Physica B 407, 2993 (2012). [2] G. Kissinger, G. Raming, R. Wahlich, T. Müller, Nitrogen doped 300mm Czochralski silicon wafers optimized with respect to voids with laterally homogeneous internal getter capabilities, Mat. Sci. Forum 725, 221 (2012). [3] K. Izunome, Advanced silicon wafers for leading-edge semiconductor devices, Proceedings of the 6th Int. Symposium on Advanced Science and Technology of Silicon Materials (JSPS Symposium), Nov. 19-23, 2012, Kona, Hawaii, USA, pp. 9-13. [4] G. Kissinger, J. Dabrowski, T. Sinno, Y. Yang, D. Kot, A. Sattler, Ab initio calculations and rate equation simulations for vacancy and vacancy-oxygen clustering in silicon, J. Cryst. Growth 468, 424 (2017). [5] G. Kissinger, M. A. Schubert, D. Kot, T. Grabolla, Investigation of the composition of the Si/SiO2 interface in oxide precipitates and oxide layers on silicon by STEM/EELS, ECS J. of Solid State Sci. and Technol. 6, N54 (2017). [6] G. Kissinger, D. Kot, M. Klingsporn, M. A. Schubert, A. Sattler, T. Müller, Investigation of the copper gettering mechanism of oxide precipitates in silicon, ECS J. of Solid State Sci. and Technol. 4, N124 (2015).

Defects in form of dislocations at the interface and threading arms in the film as well as SiGe intermixing are the main mechanisms to release the crystallographic misfit strain in Germanium (Ge) heterostructures grown on the mature Silicon (Si) wafer platform, severely deteriorating thereby the superior optoelectronic properties of Ge for device applications. We demonstrate here a novel technique, enabling fully coherent, high Ge content islands on nano-tip patterned Si (001) substrates by the suppression of plastic relaxation as well as SiGe intermixing. The Si-tip patterned substrate, fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology, features ~50 nm wide Si tips emerging from a SiO2 matrix and arranged in an ordered lattice. Molecular beam epitaxy (MBE) growths result in Ge nano-islands with high selectivity and having homogeneous shape and size. The ~850°C growth temperature required for ensuring selective growth has been shown to lead to the formation of Ge islands of high crystalline quality without extensive Si intermixing (with 91 at.% Ge). Nano-tip patterned wafers result in geometric, kinetic diffusion barrier intermixing hindrance (in particular surface diffusion suppression) confining the major intermixing to the pedestal region of Ge islands where kinetic diffusion barriers are however high. Theoretical calculations suggest that the self-assembled thin SiGe layer at the interface plays nevertheless a significant role in realizing fully coherent Ge nano-islands free from extended defects especially dislocations. Finally, single layer graphene (SLG)/Ge/Si-tip Schottky junctions were fabricated and thanks to the absence of extended defects and SiGe intermixing in the Ge islands, high performance photodetection characteristics with responsivity and Ion/Ioff ratio of ~45 mA/W and ~103, respectively, are demonstrated.

Ge is a very attractive material for optoelectronic applications and for future CMOS technologies. Therefore the creation of Ge on Si with low defect density is of great interest. Several techniques to grow high quality Ge on Si are reported e. g. in combination with cyclic annealing and etching (1, 2) or using the aspect ratio trapping technique (3). In this study, the fabrication of local GeOI structures is demonstrated by filling a lateral cavity which was formed by selective sidewall etching (4) of a mesa-patterned SiO2 / Si layer on a SOI wafer. Lateral Ge growth is carried out by using a single wafer reduced pressure CVD system. For sample preparation, epitaxial Si is deposited. The thickness of the Si on buried oxide (BOX) is targeted to 430 nm. Then wet oxidation for 300 nm is performed to produce a 300 nm thick SiO2 cap on top of 300 nm thick Si on the BOX. Top SiO2 and Si on BOX are removed by RIE dry etching to form lateral Si (010) or Si (110) surfaces at the sidewall of a mesa structure. After that, the wafer is cleaned by standard HF-last RCA cleaning. The wafer is loaded into the epi. chamber and baked at 850oC in H2 to remove residual oxide on the Si sidewalls. Then selective etching of Si by HCl is performed to form a cavity in the SiO2. After the HCl etching, Ge is deposited selectively using a H2-GeH4-HCl gas mixture. SEM is used for characterization of the deposited Ge and TEM is applied for dislocation analysis. The strain distribution is analyzed by micro Raman spectroscopy at 514 nm laser wavelength. An angle view SEM image of the sample after HCl etching is shown in Fig. 1. By HCl etching Si between the BOX and the SiO2 cap is laterally removed. The thickness loss of the BOX and the SiO2 cap are negligible indicating that the Si etching process is highly selective to SiO2. No bending is observed at the floating part of the SiO2 cap layer. At the etchfront a Si (111) facet is formed by the lateral HCl etching. A cross section TEM image of the sample after HCl etching and selective Ge growth is shown in Fig. 2. The Ge layer is selectively grown laterally on the Si surface in the cavity formed by the HCl etching. Dislocations are densely located near the interface between Si and Ge. Aspect ratio trapping (3) also works for the lateral direction, resulting in a high crystal quality Ge layer growth after ~200 nm. In Figure 3, an AFM amplitude image of a 5 µm square mesa structure with [010] sidewall direction is shown after HCl etching and lateral Ge growth followed by the removal of the SiO2 cap by HF dip. The interface between Si and Ge is visible. The root mean square of the Ge surface roughness is ~0.4 nm. It is defined by the interface roughness between Si and the SiO2cap layer. In Figure 4, a plan-view TEM image of a 5 µm square mesa structure after HCl etching and lateral Ge growth is shown. A (113) facet is observed at the growthfront of Ge. Dislocation networks are located near the Si interface. Stacking faults run only parallel or perpendicular to the [110] direction. Between them a wide area without any dislocations toward the [010] direction is observed. These results demonstrate the feasibility of the fabrication of local GeOI with high crystal quality by an additional lithography and an etching process. References 1) Y. Yamamoto et al., Solid-State Electronics 60 (2011) 2 2) Y. Yamamoto et al., Thin Solid Films 520 (2012) 3216 3) J. S. Park et al., Appl. Phys. Lett. 90 (2007) 052113 4) Y. Yamamoto et al. Thin Solid Films 517 (2008) 90

Rapid thermal annealing (RTA) is a commonly used technique to control precipitation of oxygen in Czochralski silicon wafers (1,2). RTA pre-treatment leads to the formation of intrinsic point defects, mainly vacancies, which are responsible for the enhanced precipitation of oxygen. Oxygen precipitates are widely known as getter sites for metal impurities in the silicon microelectronic technology (3). The getter efficiency of oxygen precipitates depends on their density and morphology (4,5). The density of the precipitates can be controlled by the temperature of RTA and it can be easily determined by preferential etching. The morphology of oxygen precipitates depends on the type and the concentration of dopants, the thermal history, and the annealing temperature and time (6-8). Recently, it was shown that the supersaturation of vacancies impacts the morphology of oxygen precipitates (9). Since RTA pre-treatments introduce vacancy supersaturation in silicon wafers its usage before nucleation annealing could modify the morphology of precipitates compared to wafers without RTA. The morphology of oxygen precipitates can be determined by transmission electron microscopy, however the preparation of samples is demanding. An alternative is the Fourier transform infrared (FTIR) spectroscopy at liquid helium temperature, which also allows distinguishing different types of oxygen precipitates. The oxygen precipitates give rise to absorption bands in the range between 1000 and 1300 cm-1. There are two characteristic broad bands at 1095 cm-1 and at 1225 cm-1 which belong to spherical and plate-like precipitates, respectively (10-12). The sharp bands (1136 cm-1 and satellites and 1205 cm-1) are attributed to interstitial oxygen. In this work, we investigate the morphology of oxygen precipitates by FTIR spectroscopy at liquid helium temperature and by scanning transmission electron microscopy (STEM) in silicon samples pre-treated by RTA at 1250°C for 30s in O2 containing Ar atmosphere subsequently annealed in the temperature range between 800°C and 1000°C in N2. The results show that the morphology of the oxygen precipitates in RTA pre-treated samples depends on the nucleation temperature. Fig. 1 presents absorption spectra of silicon samples pre-treated by RTA at 1250°C and annealed at 800°C (a), 900°C (b) and 1000°C (c) for 64h. As can be seen from the deconvolution of the spectra, the number and position of the bands is different for each annealing temperature. Based on the effective medium theory (EMT) (13) and STEM investigations the absorption bands can be matched to relevant morphologies.

Oxygen precipitation in Czochralski silicon is still an issue in various device technologies. On the one hand it is exploited for internal gettering of metallic impurities by oxygen precipitates and on the other hand it is undesired because oxygen precipitates are known to degrade the lifetime of minority carriers. At the end, it depends on the application of the silicon material how precipitation of interstitial oxygen is controlled. The reduced thermal budgets due to continuous scaling of features sizes in high end device technologies lead to the development of faster and faster anneal processes. The earlier device technologies were dominated by conventional annealing processes. Today rapid thermal processes working on the second scale are common steps in microelectronic processing. Recent developments utilize already thermal processes on the millisecond scale as e. g. flash and laser anneals. All these different time scales influence the generation of intrinsic point defects and thus also the kinetics of oxygen precipitation in a different way. Rapid thermal annealing (RTA) is a widely used thermal pretreatment to create an internally gettering bulk defect zone and a defect denuded zone below the surface. This is possible because the precipitation of interstitial oxygen strongly depends on the supersaturation of intrinsic point defects. During RTA vacancies supersaturate facilitating the formation of VmOn complexes which are the initial stages of oxygen precipitation. However, the strength of the effect depends on the temperature and cooling rate of the RTA pre-treatment. Flash lamp annealing is used first of all for the creation of shallow dopant profiles in high end electronic device technologies. The surface of a silicon wafer can be heated with this technique to temperatures up to the melting point within a few milliseconds. With the help of a thermal model we can simulate the temperature profiles. We combined this model with a second model describing the generation and annihilation of intrinsic point defects. The results of modeling help to understand the experimental results of oxygen precipitation. After 3 ms of annealing a defect denuded zone below the front surface is generated while after 20 ms annealing oxygen precipitation is suppressed in the wafer. Flash lamp annealing leads to steep temperature profiles in the wafers causing stress. Silicon wafers with etched, ground, and sawed surfaces were subjected to flash lamp annealing for 20 ms. Such wafers contain different densities of pre-existing dislocations which propagate into the wafer during flash lamp annealing up to a certain depth which is different on the front and back sides. Plastic deformation was not observed if no pre-existing dislocations were present in the wafer before flash lamp annealing. The elastic and plastic deformation was simulated by a mechanical model. In summary, the difference between thermal processing on the second and on the millisecond scales is based on the temperature profiles generated by the different types of processing. These profiles influence the shrinking of grown-in oxide precipitate nuclei and the generation, diffusion, and annihilation of intrinsic point defects and thus the oxygen precipitation during further processing.