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Ga2O3 has exploded onto the semiconductor landscape for next-generation power electronics because its enticing material properties, most notably a large critical field strength stemming from its ultra-wide bandgap of 4.5 eV, promise miniaturized circuits and systems with high conversion efficiency. High-quality native substrates produced by melt-growth methods offer an economical platform to this technology. Ga2O3 transistors reported to date have predominantly taken on a lateral geometry, yet vertical switching devices are desirable for applications that demand high voltage ratings and high power levels since they allow for large current drives, simplified thermal management, and superior field termination. Capitalizing on cost-effective ion implantation technologies for shallow donor (silicon) and deep acceptor (nitrogen) doping of Ga2O3 with efficient dopant activation at a low thermal budget, we developed both depletion-mode (D-mode) [1] and enhancement-mode (E-mode) [2] current aperture vertical Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs). The vertical Ga2O3 MOSFETs were fabricated on low-doped (~1016 cm-3) halide vapor phase epitaxial drift layers grown on single-crystal β-Ga2O3 (001) substrates [3]. In these devices, silicon ion-implanted top source contacts were electrically isolated from the bottom drain contact by a nitrogen ion-implanted current blocking layer (CBL) [4] except at an aperture bounded by CBLs through which drain current was conducted. The CBL simultaneously served as a back-barrier for a top-gated lateral channel defined by another silicon ion implantation step. D-mode devices delivered a drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 mΩ·cm2, and an output current on/off ratio of over 108. E-mode devices, whose positive threshold voltage was attained by appropriately designing the channel doping concentration such that the channel was fully depleted at 0-V gate bias, showed a high output current on/off ratio of 2×107 despite a nonideal MOS interface that limited the maximum drain current density to 2. Both D-mode and E-mode devices did not exhibit current collapse in pulsed measurements when subjected to off-state voltage stress; however, their hard breakdown occurred prematurely owing to leakage through the CBLs, a deficiency expected to be readily overcome with an optimized nitrogen implantation process. Further details regarding fabrication, performance, and physics of the devices, as well as potential directions for future development, will be discussed in the talk. The demonstration of planar-gate vertical Ga2O3 transistors based on a highly manufacturable all-ion-implanted process greatly enhances the prospects for Ga2O3-based power electronics applications. [1] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, 431 (2019). [2] M. H. Wong, H. Murakami, Y. Kumagai, and M. Higashiwaki, Proc. 77th Device Research Conference (2019). [3] H. Murakami, K. Nomura, K. Goto, K. Sasaki, K. Kawara, Q. T. Thieu, R. Togashi, Y. Kumagai, M. Higashiwaki, A. Kuramata, S. Yamakoshi, B. Monemar, and A. Koukitu, Appl. Phys. Express 8, 015503 (2015). [4] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018).

As a key ultra-wide bandgap semiconductor, gallium oxide (Ga2O3) has been attracting much interest for power device applications due to its excellent material properties based on an extremely large bandgap of 4.5 eV and the availability of high-quality, large-diameter wafers produced from bulk single crystals synthesized by melt growth methods. Despite having received only little attention, the ease of both n- and p-type ion implantation doping is another very attractive and important feature for Ga2O3 device technologies. Recently, we succeeded in developing nitrogen (N)-ion implantation doping technology to form p-type Ga2O3 [1]. Note that it is almost impossible to obtain p-type Ga2O3 with effective hole conductivity as for conventional semiconductors. This is not only due to a lack of shallow acceptors with moderate activation energies but also because the valence band structure of Ga2O3, which is composed of O 2p orbitals, is characterized by a very large hole effective mass and conduces to self-trapping of holes with associated characteristic lattice distortions. Therefore, p-Ga2O3 is only useful for engineering large energy barriers in the form of p-n junctions. We have experimentally confirmed that a N-ion implanted p-Ga2O3 region formed in n-Ga2O3 can be utilized as a current blocking layer. In this talk, we first discuss the material properties of p-Ga2O3 formed by N-ion implantation doping. Then, the device process and characteristics of vertical normally-on Ga2O3 MOSFETs fabricated by using multiple Si- and N-ion implantations are presented [2]. This work was partially supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: New Energy and Industrial Technology Development Organization). [1] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018). [2] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, 431 (2019).

The groundbreaking demonstration of the first single-crystal gallium oxide (Ga2O3) transistors in 2011 galvanized intensive international research activities into the science and engineering of this new oxide semiconductor [1]. Much of the research and development has been motivated and inspired by the unique material properties of Ga2O3 based on an extremely large bandgap of 4.5 eV and the availability of large-size, high-quality, affordable single-crystal wafers produced from melt-grown bulk crystals. For the past several years, world-wide efforts on the development of Ga2O3 transistors have mostly been devoted to lateral field-effect transistors (FETs). However, as is well known, a vertical device geometry is much more suitable for high-voltage and/or high-current applications than a lateral geometry, because the former allows for high current drives without having to enlarge the device chip size, simplified thermal management, and far superior field termination. In this talk, we will present our state-of-the-art vertical Ga2O3 FET technologies. We fabricated depletion-mode vertical Ga2O3 metal-oxide-semiconductor FETs (MOSFETs) with a current aperture formed by buried current blocking layers (CBLs) [2]. The devices were fabricated on a 5-µm-thick n-Ga2O3 drift layer with a Si doping density of 2.5×1016 cm-3 grown by halide vapor phase epitaxy (HVPE) on an n +-Ga2O3 (001) substrate [3]. Three ion implantation process steps were employed to form Si-doped n +-regions (Si=5×1019 cm-3, 0.1-µm-thick box profile) for the source ohmic contacts, a Si-doped n-channel (Si=1.5×1018 cm-3, 0.15-µm-thick box profile), and nitrogen (N)-doped p-type CBLs in the HVPE drift layer. N was ion-implanted at an energy of 480 keV and a dose of 4×1013 cm-2, followed by thermal annealing at 1100°C for activation. Note that we found that N atoms doped in Ga2O3 act as deep acceptors to compensate background electrons, and that our development of the N-ion implantation doping process was a technological breakthrough [4], which would lead to the fabrication of planar-gate vertical MOSFETs. The current aperture vertical MOSFET showed decent device characteristics such as a maximum drain current density of 0.42 kA/cm2, a specific on-resistance of 31.5 mΩ·cm2, and a high drain current on/off ratio of over eight orders of magnitude. The off-state breakdown voltage was limited to less than 30 V owing to the large electric field in the Al2O3 gate dielectric, but can be increased by improving material quality of the gate dielectric and optimizing doping schemes. This work was partially supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics” (funding agency: New Energy and Industrial Technology Development Organization). [1] M. Higashiwaki, K. Sasaki, A. Kuramata, T. Masui, and S. Yamakoshi, Appl. Phys. Lett. 100, 103504 (2012). [2] M. H. Wong, K. Goto, H. Murakami, Y. Kumagai, and M. Higashiwaki, IEEE Electron Device Lett. 40, in press (2019). [3] K. Goto, K. Konishi, H. Murakami, Y. Kumagai, B. Monemar, M. Higashiwaki, A. Kuramata, and S. Yamakoshi, Thin Solid Films 666, 182 (2018). [4] M. H. Wong, C.-H. Lin, A. Kuramata, S. Yamakoshi, H. Murakami, Y. Kumagai, and M. Higashiwaki, Appl. Phys. Lett. 113, 102103 (2018).

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj¬5x1019cm-3, ρc= 6 Ω.µm2 and Dit = 4 x 1012 eV-1.cm-2.

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High electron mobility III-V materials are strong candidates for nMOS transistors at the 11 nm technology node and beyond. Integrating III-V materials with Si (III-V/Si) is an attractive approach because it leverages the current Si-based manufacturing platform. However, the large lattice mismatch between III-V and Si leads to defects in the channel and compromises device performance and reliability. This paper explores two inline X-ray based characterization techniques, high resolution X-ray diffraction (HRXRD) and X-ray diffraction imaging (XRDI), to characterize defects in novel III-V/Si structures. The benefits and limitations of these techniques will be discussed.