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Strained SiGe and SiC sources and drains are planned to be used in sub-28nm FDSOI devices in order to improve the carriers mobility. Consequently, silicide-induced relaxation of strained epitaxial layers is a key issue to address in order to fully benefit from the desired effects of strain engineering techniques. This paper deal with the impact of the silicidation process conditions on the strain of Si1-xGex:B layers (x=0.3 and 0.45) and SiC:P with [C]≤1,5%. We show that the strain of epitaxial layers is not affected by the silicidation in the case of Si0.7Ge0.3 and SiC, while a strong degradation of strain occurs with Si0.55Ge0.45. The strain evolution in the channel of a device at various stages of the silicidation process has been followed using dark field electron holography. We show that process parameters can be tuned in order to minimize the reduction of strain induced by the silicidation

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress to the sub 10 nm nodes level and face the challenge to approach zero variability. The main requirements will be to reduce leakage currents and reduce access resistances at the same time in order to fully exploit 3D integration at the device, elementary function, chip and system. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible

To improve 20nm FD-SOI pMOS transistor performances, salicide process must be optimized on SiGe source&drain. In this paper, we propose an investigation on Ni and Pt/Si1-xGex (x=0.15, 0.3) systems. In a first part, process window is studied to determine thermal budget domain where the less resistive phase is stable morphologically and thermically. Solid state reactions in terms of phase sequence, thermal stability and morphology have been examined. At high temperature, two kinds of degradations have been observed. In Ni case, Ge out diffusion leads to the film agglomeration. In Pt case, grain coalescence degrades germanosilicide film. In a second part, contact resistivity has been extracted on lateral germanosilicides thanks to new designed structures. After a validation on Pt/Si system, RC extraction has been carried out on Si1-xGex substrate up to 30% of Ge. RC seems to be better with Pt compared to Ni with the same conditions of process optimizations.

The problematics of contacts optimization on Germanium MOSFETs suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals such as Ti on Ge were so far mostly investigated on weakly n-doped samples under pure Thermionic Emission (TE) regime. In this paper, we detail Schottky Barrier Height (SBH) extractions based on contact resistance (Rco) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully-processed GeOI samples with Ti-based contacts, yielding effective barriers of 0.32eV for electrons and 0.15eV for holes. The method provides a good physical understanding of the technological factors impacting their electrical properties, therefore enabling to define paths towards ohmic contact optimization in the context of device integration on GeOI.

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (

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The problematics of contacts optimization on germanium metal-oxide-semiconductor field-effect transistors suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals on Ge were so far mostly investigated on weakly n-doped samples under the pure thermionic emission regime. These experimental conditions are suitable for an accurate extraction; the measured Schottky barrier height (SBH) being usually large and linked to the interfacial current density by a relatively simple Arrhenius relationship. However, a device-oriented approach would consist in meeting the contact resistivity requirements in the ohmic regime for metallic contacts on a highly doped semiconductor (e.g., doped source and drain) through the choice of metal, interface preparation, and doping conditions. We hereby detail SBH extractions based on contact resistance (R co ) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully processed germanium-on-insulator (GeOI) samples with Ti-based contacts, yielding effective barriers of 0.32 eV for electrons and 0.15 eV for holes. The method provides a good physical understanding of the technological factors impacting the electrical properties, enabling to define paths toward ohmic-contact optimization in the context of device integration on GeOI.

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