Search

Spike-based neural networks have been shown to hold more computational power than other architectures and their integration into mainstream computing is projected to herald a new age for information technology. Implementation using a flexible Thin Organic Large Area Electronics TOLAE process is a promising low cost way to integrate neuromorphic circuits into sensors, however its feasibility has never been demonstrated. Here we simulate spiking neuron circuits based on the characteristics of a gravure printed scalable organic thin film transistor technology. We then explore the variability of the parameters to show how much variation the circuits can support. Our results demonstrate the feasibility of OTFT technologies for spiking neuromorphic hardware. Figure 1

We study the low frequency noise, also known as flicker noise (1/f), in polymer-based Organic Thin Film Transistors, and we review techniques to identify the mechanisms of the 1/f noise based on a specific model of the device. We found that the quality of the gate dielectric and its interface may determine the dominant noise mechamism. Three theories have been formulated to explain the origin of 1/f noise in FET devices: the carrier number fluctuation (∆N) theory[1], the mobility fluctuation (∆µ) theory [2], and the ∆N - ∆µ theory [3], which assumes that effects of insulator charge fluctuations affect the carrier mobility at the interface. The ∆N - ∆µ theory reduces to the ∆N model when the surface mobility is not affected by carrier number fluctuation. According to the ∆N - ∆µ theory [3]the plot of SID(f)/ID 2 and [gm/ID]2 against ID (gm being the transconductance and ID the drain current) allows us to identify the noise mechanism. When both curves are parallel, 1/f noise must be due to carrier number fluctuation. If there is a slight deviation from this parallel behavior, it must be due to the correlated surface mobility fludtuation (∆N - ∆µ model). A number of analysis of the noise in OTFTs have been published. In most of them, it is found to be a bulk phenomenon[4,5], and as a result the main mechanism is assumed to be mobility fluctuation. However, very often these analysis are not very complete and are based on crystalline MOSFET models instead of specific OTFT models. On the other hand, it was demonstrated that the analysis must be made over a range wide of bias in order to accurately determine the origin of noise [6,7]. We studied the origin of 1/f noise two polymeric p-type OTFT technologies developed by CEA´Liten (France). We found that in the older technology the slopes, in log-log scale, of SID(f)/ID 2 and [gm/ID]2, versus ID had quite different values. This means that the main mechanism of noise in OTFTs is not the fluctuation of the number of carriers. Plotting SID(f)/I2 Dvs (VGS-Vth) in log-log scale (Vth being the threshold voltage) for devices with different channel lengths, channel width W=2000 µm and at VDS = 1 V, we observed that the extracted slope is close to -1 (Table 1). This indicates that noise is due to the fluctuation of carrier mobility, due to the lower quality of the materials and fabrication defects. The threshold voltage was extracted assuming a physically-based OTFT model with a power-law based model of the field effect mobility [8]. In the second technology, mobility values are higher, 2-3 cm2/(V s). The normalized current noise PSD follows the squared-transconductance ratio variation (Fig. 1), not the inverse of the drain current. We concluded that the low frequency in the targeted devices of the second technology is originated from the carrier number fluctuation due to trapping/release of charge carriers by trap states uniformly distributed within the gate oxide. The extracted values of gate dielectric trap-states density are comparable to values obtained in conventional Si-based MOSFETs [7], indicating the higher quality of the gate dielectric and its interface with the polymeric material compared to the first studied technology and other previously reported OTFT devices. [1] McWhorter A. L.. "1/f noise and germanium surface prosperities," Semiconductor Surface Physics. R. H. Kingdton (Ed), University of Pennsylvania Press, Philadelphia, PA, 1957, pp. 207-228. [2] Hooge F. N., "1/f noise is no surface effect", Physics Letters, 29A (3), 1969, 139–140 [3] Ghibaudo, G., et al..,‘Improved analysis of low frequency noise in field-effect MOS transistors’, Phys. Status Solidi. A , 1991, 124, pp. 571-581 [4] L. Ke, S., et al., “Low frequency noise analysis on organic thin film transistors,” Journal of Applied Physics 104, 124502 (2008). [5] H. Kang and V. Subramanian, “Measurement and analysis of 1/f noise under switched bias in organic thin film transistors,” Applied Physics Letters 104, 023301 (2014). [6] Y. Xu, et al., “Origin of low-frequency noise in pentacene field-effect transistors,” Solid-State Electronics 61, 106–110 (2011). [7] W. E. Muhea, et al.. “1/f noise analysis in high mobility polymer-based OTFTs with non-fluorinated dielectric,” Appl. Phys. Lett. 114, 243301 (2019). [8] C.H. Kim; et al., “A Compact Model for Organic Field-Effect Transistors With Improved Output Asymptotic Behaviors,” IEEE Trans. on Electron Devices, vol. 60, no. 3, pp. 1136-1141, March 2013. Figure 1

Organic TFTs (OTFs) are very promising devices for flexible, wearable and printed electronics. Nowadays OTFT performances are already comparable to a-Si:H TFTs. In order to design OTFT circuits, physically-based compact models for the OTFT DC, AC and transient characteristics are needed. This requires a correct understanding of the physical effects affecting OTFT behavior. Despite a number of compact I-V models have been presented, only a few C-V models have been published [1-4]. Besides, very few models have considered the temperature dependence, even though temperature analysis is instrumental to identify relevant physical effects. Moreover, most of those temperature studies have been carried out only for I-V characteristics at high temperatures [5] and the very few analysis at low temperatures have not targeted all parameters [6]. In this work, we present a complete study of both current and gate capacitance in OTFTs for temperatures ranging from 150K to 350K. Parameters were extracted using a unified model and extraction method specific to OTFTs, based on assuming an exponential DOS and variable range hopping [7-8]. The dependences of model parameters with the temperature are analyzed. In order to carry out the temperature study of C-V characteristics, we improved an analytical capacitance model [1, 3] for OTFTs in order to be valid from the depletion to the accumulation regime with continuous and smooth regime transitions as well as for the first order gate capacitance derivative. The key parameters used in the capacitance model are the same as those of I-V characteristics and were extracted from them [4, 7]. Furthermore, we show that from the first order gate capacitance model derivative, we can identify the different operating regimes and obtain the threshold voltage () and band-flat voltage ( at different temperatures. We performed measurements on small-molecule OTFTs manufactured in CEA-Liten (Grenoble- France). The OTFTs under study were top gate bottom contact multifingers with and. Our model shows good agreement with the experimental I-V (Fig. 1) and C-V (Fig. 2) characteristics, and the first order capacitance model derivative (Fig. 3) from for temperatures ranging from 120K to 350K, and for frequencies up to 10 kHz. [1] Castro-Carranza, A., et al., (2012). Organic thin-film transistor bias-dependent capacitance compact model in accumulation regime. IET circuits, devices & systems, 6(2), 130-135 [2] Li, L., Marien, et al.,, “Compact Model for Organic Thin-Film Transistors” IEEE Electr Dev Let, vol. 31, no. 3, pp. 210-212, Mar. 2010. [3] Fadlallah, M., et al. “Modeling and characterization of organic thin film transistors for circuit design” J. Appl. Phys, vol. 99, no.104504, May 2006. [4] Estrada, M., et al.,(2013). Frequency and voltage dependence of the capacitance of MIS structures fabricated with polymeric materials. IEEE Transactions on Electron Devices, 60(6), 2057-2063. [5] Estrada, et al., (2010). Modeling the behavior of charge carrier mobility with temperature in thin-film polymeric transistors. Microelectronic Engineering, 87(12), 2565-2570. [6] Haddad, C., et al., Organic Electronics (2018), https://doi.org/10.1016/j.orgel.2018.06.037 [7] Estrada, M., at al., (2005). Accurate modeling and parameter extraction method for organic TFTs. Solid-state electronics, 49(6), 1009-1016. [8] Estrada, M.,et al., . (2008). Mobility model for compact device modeling of OTFTs made with different materials. Solid-State Electronics, 52(5), 787-794. Figure 1

Organic-inorganic hybrid quantum dot (QD) based light emitting diodes (LEDs) have been investigated. Stacked hybrid QD LED structures, based on cadmium selenide QD with cadmium sulfide barrier shells, have been fabricated at the Universtiat Rovira i Virgili using spin coating techniques. These have been modelled, with Technology Computer Aided Design (TCAD) software, using two different carrier conduction models. Two quantum confinements models are used to predict the electronic transport through these stacks. A 1D simulation of a stack with a single QD mono-layer, using the Silvaco Radiant tool based on the Atlas engine, is reported. This approach allows device designers to optimise the current density and spectral response as a function of QD radius (as shown in the figure) and transport layer thicknesses. Furthermore, a second approach using a 3D QD simulation in which the user can investigate the effect of the QD radius and barrier layer thickness on the carrier confinement in the structures is shown. This work demonstrates the capability of 1D simulations, using the Radiant software tool, to model the behavior of single QD mono-layer structures. The user friendly input graphical user interface, as well as the speed of the simulation, helps to iterate the design quickly to optimise QD size and transport layer thicknesses for maximum intensity at the desired spectral output. Figure 1

This paper complements our new compact analytical model for long and short channel symmetric double-gate MOSFETs, which for the first time, considered a doped silicon layer in a wide range of concentrations, between 1014 and 3x1018 cm-3. The already incorporated short channel effects that included threshold voltage variation, DIBL, channel shortening and saturation velocity were further revised and the series resistance effect was included. The model uses the charge control procedure, where the mobile charge density is modeled as function of silicon layer impurity concentration; gate dielectric and silicon layer thickness and applied voltages. Comparison of modeled and simulated (using the ATLAS device simulator) transfer characteristics in linear and saturation regions, as well as output characteristics, shows a good agreement within the practical range of gate and drain voltages and silicon layer doping concentrations.

The conjugated polymer Poly (3-Hexylthiophene) (P3HT) has attracted much attention as material for the fabrication of Organic Thin Film Transistors (OTFTs) because of its relatively high mobility. However, it has been reported that P3HT increases its conductivity when it is exposed to air or oxygen. In this paper, we studied the change in conductivity of P3HT layers annealed at different temperatures and atmospheres and demonstrate that the increase in conductivity of the P3HT layers after long exposure to air and N2 can be returned to its original value after annealing the device at 363 K in O2 at a pressure of 39.99 Pa (0.3 torr) for 30 min. The procedure was applied to OTFTs fabricated with Poly (3- Hexylthiophene) (P3HT) as active layer and Poly Methyl Methacrylate (PMMA) as dielectric, which were left to long exposure to air and N2, observing that their electrical characteristics returned exactly to their initial values.

We describe the compact model that captures the new physics involved in Thin Film Transistors with non-ideal contacts, where the contact itself controls the carrier density under the contact. Such a contact could be modeled as a non-linear transmission line consisting of thin film transistors with leaky gates. However, we show that the compact model that incorporates a contact thin film transistor and non-ideal diodes can adequately describe experimental data, such as dependencies of field effect mobility on the gate length for different materials systems ranging from amorphous silicon to organic semiconductors. The model can also describe the capacitance-voltage characteristics and suitable for implementation in circuit simulators, such as AIM-Spice.

not Available.

not Available.

not Available.

The behavior of single and double gate accumulation mode silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) is thoroughly investigated. Accumulation mode devices present advantages over inversion mode transistors regarding transconductance, ease of fabrication, and parasitic effects. We have concluded, from experimental results and 2D simulations, that short channel effects such as DIBL and subthreshold swing degradation are substantially reduced in the volume accumulation regime, being even lower in thin-film double gate accumulation mode SOI MOSFETs than in inversion mode double gate SOI devices for adequate technological characteristics. The potential of thin-film accumulation mode SOI MOS transistors down to sub-0.1 mum technologies and up to 125 degrees C is demonstrated. (C) 2001 The Electrochemical Society.