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When solving nonlinear algebraic equations that arise from discretization using the finite element method (FEM), it is often observed that the standard Newton-Raphson (N-R) iteration either fails to converge or necessitates a large number of iterations in the vicinity of critical points. This work proposes an additional numerical strategy, known as the Potra-Pták iterative cycle, to improve the efficiency of solving highly nonlinear structural problems. Therefore, the focus here is on making the nonlinear solver more robust and efficient, allowing the analysis of more complex nonlinear structures. In the Potra-Pták iterative cycle, two corrections of the objective function (energy function) are performed. The introduction of a second correction in the iterative cycle makes the Potra-Pták strategy more efficient than the standard or modified N-R iterations. This numerical strategy was implemented in the homemade Computational System for Advanced Structural Analysis (CS-ASA) program. The program is based on the FEM and is capable of performing static and dynamic nonlinear analysis of steel, concrete, and composite structures, and its efficiency is then verified through the analysis of slender frames and arches. The algorithm details for solving the nonlinear structural problem, characterized by the Potra-Pták scheme, are provided. [ABSTRACT FROM AUTHOR]

Multilayer (14 layers, 115–122 nm thick each) BiFeO3/CoFe2O4/substrate (BFO/CFO) and CoFe2O4/BiFeO3/substrate (CFO/BFO) nanocomposites were obtained by the method of sol-gel synthesis. It is shown that all samples of the obtained nanocomposites have multiferroic properties at room temperature. At the same time, there is a clearly demonstrated effect of the layering order on the values of remnant polarization and magnetization of these samples. This influence originates from the much smaller size of the crystallites in the BiFeO3 layers for the samples deposited in order (BFO/CFO) at various annealing temperatures (700, 725, and 750 °C). [ABSTRACT FROM AUTHOR]

This paper presents the design and experimental results of a clock generator for high-frequency, continuous-time,converters. The circuit was fabricated in a-V,-nm CMOS technology along with twomodulators intended for the digitisation of UWB signals. The clock generator is based on a PLL frequency synthesiser with a low phase noise LC Voltage-controlled oscillatror (VCO). This kind of oscillator achieves the required low jitter specification with a substantial lower power consumption than a conventional ring VCO. In order to save die area, the VCO was made to operate at four times the desired clock frequency ofMHz, and a compact multi-layer inductor was used. A system clock with a cycle-to-cycle jitter of onlyof its period is obtained. The total circuit area isand the resulting power consumption is. [ABSTRACT FROM AUTHOR]

In this article a current-mode, second-order, CT Sigma-Delta modulator operating at a sampling frequency of 25 MHz and with an oversampling ratio of 64 has been designed. The modulator consists of current-mode, differential integrators based on a single-stage folded cascode topology and switched capacitors DACs cells generating exponential feedback waveforms. The modulator was analysed in detail from both a system- and a circuit-level point of view. A 'short' exponential DAC pulse, namely, an exponential pulse whose time constant is lower than the pulse width, was used to improve jitter rejection. Modulator feedback coefficients were analytically derived for an exponential feedback waveform. Jitter considerations paying special attention to its impact on CT Sigma-Delta modulators were presented, and two different contributions distinguished: independent jitter and accumulated jitter. Finally, functional- and transistor-level simulations have been accomplished to obtain significant features of the modulator performance. [ABSTRACT FROM AUTHOR]

A very low voltage solution for the realization of the hold capacitor in a Track&Hold circuit based on an open-loop architecture is introduced. The circuit is a modification based on the switched opamp approach of the Track&Hold circuit using Miller Capacitance. Simulations show that the circuit is able to operate at 1V 1MS/s with a Total Harmonic Distortion of -64 dB @ 100 kHz and a very low power consumption of 80 µW. [ABSTRACT FROM AUTHOR]