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A novel approach utilising the emerging memristor technology is introduced for realising a 2-input primitive XNOR gate. This gate enables in-memory computing and is used as a building block of multi-input XNOR gates. The XNOR gate is realised with eight memristors of two crossbar arrays. The average power consumption of an 8-input XNOR gate is calculated and compared with its counterpart realised with CMOS technology – the XNOR gate consumes less power. ESOP realisation can be directly implemented with XNOR gates. Our simulation results and comparisons show the benefit of the proposed XNOR gate in terms of delay, area, and power. Volistor logic XNOR gate. (a) Circuit diagram of two-input volistor logic XNOR gate. Input voltages are applied to memristors S1 and S2 through horizontal wires Win1 and Win2, and the output which is logical AND of states S1 and S2 is calculated by applying VREAD to vertical wire WXNOR. (b) Block diagram of two-input volistor logic gate. (c) A multi-input volistor logic XNOR gate can be implemented by connecting two XNOR gates though CMOS switches. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model of double-gate MOSFET architecture including ballistic and quasi-ballistic transport down to 20 nm channel length. In addition, this original model takes into account short-channel effects (SCE/DIBL) by a simple analytical approach. The quasi-ballistic transport description is based on Lundstrom's backscattering coefficient given by the so-called flux method. We also include an original description of scattering of processes by introducing the 'dynamical mean free path' formalism. Moreover, we implemented our model in a Verilog-A environment, and applied it to the simulation of circuit elements such as CMOS inverters and ring oscillators to analyse the impact of ballistic/quasi-ballistic transport on circuit performances. Finally, in order to validate our work, we confronted this model with numerical simulation of CMOS and ring oscillator in ballistic case. [ABSTRACT FROM AUTHOR]

Up to date, MOSFETs have been made through well established techniques that use SiO2 as the gate dielectric and the related design issues are well established. The need to scale down device dimensions allowed researchers to seek for alternative materials, in order to replace SiO2 as the gate dielectric. The implementation of such MOS devices in memory or logic circuits needs to take into account the effects that the use of the new gate dielectrics has on parameters such as the threshold voltage and the drain current. Hence, parameters such as the high dielectric constant values, extra oxide charges and process related defects at the physical level must be taken into account during the device design. As far as circuit applications are concerned, these changes may substantially affect the required performance. This paper presents and provides proposals about the issue of replacing commonly used parameters of the MOSFET modelling with new parameters, in which the presence of a gate dielectric with different properties from those of SiO2 is taken into account. A stepwise procedure is described for the new device design. Moreover, a case study is presented which examines a memory circuit built up by such new technology devices. In particular, this paper presents and analyses the design of a DRAM cell made up of MOSFETs with an alternative gate dielectric. The 90 nm technology and the BSIM4 model equations are used to derive the single MOSFET behaviour and subsequently the DRAM circuit performance. The results are analysed and compared to those obtained from conventional SiO2 devices. A cell layout is provided and the DRAM circuit characteristics are also presented. [ABSTRACT FROM AUTHOR]

This paper presents results of work to explore the feasibility of using resonant tunnelling diodes (RTDs) and conventional MOSFETs for the development of digital logic circuits. Based on the use of RTDs and MOSFETs, two different logic design styles fixed pull-down and fixed pull-up are proposed and evaluated. Fixed pull-up gates perform better than their CMOS counterparts with similar device sizes. Since the proposed fixed pull-down style avoids the use of series MOSFETs, for large fan-in gates it yields significantly better performance than the corresponding CMOS gates. [ABSTRACT FROM AUTHOR]

Introduces various kinds of basic complementary metal oxide semiconductor four-valued logic circuits that can employed for circuits with clock pulses. Development of design of multiple-valued logical-sum (MAX) and logical-product circuits with many inputs; Model parameters of metal oxide semiconductor transistors used; Comparison between quaternary MAX circuit and equivalent binary one.