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6. Accurate and Efficient Evaluation of the Transient Response in RLC Circuits: The DTT Method

Author

Eby G. Friedman and Yehea Ismail

Subjects
Reduction (complexity), High fidelity, Computer science, law, SIGNAL (programming language), Electronic engineering, RLC circuit, Elmore delay, Transient response, Integrated circuit, Transfer function, Hardware_LOGICDESIGN, law.invention
Abstract

Several popular methods for evaluating the transient response of integrated circuits have been discussed in Chapter 3. The Elmore and Wyatt approximations for RC trees are discussed in 3.1. An equivalent Elmore delay model for RLC trees is presented in Chapter 7. These models are used as fast, low accuracy approximations of the delays within a high complexity integrated circuit. The computational speed of these delay models makes these models appropriate for analyzing large integrated circuits in a reasonable time in order to determine approximate delay estimates. The high fidelity of these delay models also makes these models appropriate for design methodologies where an efficient solution is required. However, high accuracy characterization and simulation of the interconnect behavior and signal transients are required for analyzing performance critical modules and nets and to accurately anticipate possible hazards during switching. Also, increasing performance requirements have forced a reduction of the safety margins used in the design of worst case signal paths, requiring more accurate interconnect delay characterization.

Published
2001
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