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Assuring correctness of digital designs is one of the major tasks in the system design flow. In the last decade, traditional functional verification techniques like simulation with test benches and monitors have been augmented with formal techniques. Formal techniques can be divided into equivalence and property checking. Equivalence checking tools at the gate level are now part of most design flows. However, property checking is still subject to intensive research efforts due to the omnipresent state explosion problem.

In this paper we present a new model checking algorithm for interval based timed structures and temporal logic formulas. Besides the treatment of time intervals the new algorithm leads to a significant performance gain compared to previous approaches.