64 results on '"FinFET"'
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2. Performance Assessment of High-k SOI GaN FinFET with Different Fin Aspect Ratio for RF/Wireless Applications
3. An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET
4. Three-dimensional quantum-corrected Monte Carlo device simulator of n-FinFETs
5. Reliable and ultra-low power approach for designing of logic circuits
6. Exploring the Potential of Dielectric Modulated SOI Junctionless FinFETs for Label-Free Biosensing
7. Low Power and Suppressed Noise 6T, 7T SRAM Cell Using 18 nm FinFET
8. Design of a 10-nm FinFET 11 T Near-Threshold SRAM Cell for Low-Energy Internet-of-Things Applications
9. An efficient technique to predict DC characteristics of nano-FinFETs using a deep neural network
10. Nano-scale optical guidance and control in finfet like structure
11. FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nm
12. A Novel Low Power 4:2 Compressor using FinFET Devices
13. A Schmitt-Trigger-Based Low-Voltage 11 T SRAM Cell for Low-Leakage in 7-nm FinFET Technology
14. Effects of Random Nanosized TiN Grain on Characteristic of Gate-All-Around FinFETs with Ferroelectric HZO Layer
15. Process evaluation in FinFET based 7T SRAM cell
16. An improved model to predict DC characteristics of organic field-effect transistors
17. DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications
18. Ultra-Compact Imprecise 4:2 Compressor and Multiplier Circuits for Approximate Computing in Deep Nanoscale
19. Design and Simulation for NBTI Aware Logic Gates
20. Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects
21. Capacitance matching by optimizing the geometry of a ferroelectric HfO2-based gate for voltage amplification
22. Performance analysis for reliable nanoscaled FinFET logic circuits
23. Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique
24. A single-ended low leakage and low voltage 10T SRAM cell with high yield
25. Two-dimensional modeling of the underlap graded-channel FinFET
26. Relative Study of Analog Performance, Linearity, and Harmonic Distortion Between Junctionless and Conventional SOI FinFETs at Elevated Temperatures
27. Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects
28. Energy-efficient magnetic 5:2 compressors based on SHE-assisted hybrid MTJ/FinFET logic
29. A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology
30. Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects
31. Threshold voltage modeling for a Gaussian-doped junctionless FinFET
32. Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops
33. 3D numerical simulations of single-event transient effects in SOI FinFETs
34. Efficient ab initio analysis of quantum confinement and band structure effects in ultra-scaled Si1−xGex gate-all-around and fin field-effect transistors for sub-10 nm technology nodes
35. Temperature-dependent short-channel parameters of FinFETs
36. Gate Oxide Short Defect Model in FinFETs
37. Design and structural optimization of junctionless FinFET with Gaussian-doped channel
38. Design of Low-Power High-Performance FinFET Standard Cells
39. Making use of semiconductor manufacturing process variations: FinFET-based physical unclonable functions for efficient security integration in the IoT
40. A technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture
41. Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits
42. Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power
43. A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology
44. Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies
45. Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance
46. A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design
47. Gate and drain SEU sensitivity of sub-20-nm FinFET- and Junctionless FinFET-based 6T-SRAM circuits by 3D TCAD simulation
48. A two-dimensional (2D) analytical surface potential and subthreshold current model for the underlap dual-material double-gate (DMDG) FinFET
49. A novel laminated gate to improve the ON-state resistance of LDMOS transistors
50. A two-dimensional (2D) analytical surface potential and subthreshold current model for underlap dual-material double-gate (DMDG) FinFET
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