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The Fourier Transform is a noteworthy calculation in digital signal processing region. An enhanced signal flow graph is required for FFT processor structures, whose sources of information and outputs are in normal order. In this paper, a memory-based conflict-free FFT processor design by utilizing a modified radix-8 DIF (Decimation-In-Frequency) signal flow graph is proposed. The number of iterations is decreased, and therefore, the execution time is low when compared with memory-based radix-4 FFT. The architecture is implemented on Xilinx Virtex-6 FPGA platform. The proposed FFT processor with radix- 8 has reported lower processing time when compared with radix-4 FFT processor.

In any real-time application, overall system performance is characterized by accuracy in arithmetic used for computation and its ability to support low-cost hardware implementation. Accordingly, optimization methods for floating point computation have emerged owing to improved precision level. In particular, for floating point FFT computation, hardware complexity reduction is prerequisite to narrow down the complexity penalty gap between fixed and floating point FFT models. In this, initially, application-dependent hardware fusion units are modeled to improve the hardware utilization rate during FPU arithmetic computations. Afterwards, reconfigurable CSD-driven integer multiplication is proposed for mantissa computation which precisely reduces the hardware count. Finally, radix factorization is incorporated to reduce complex arithmetic involved in FFT stages. Results show that the algorithm proposed ensures area reduction, operating frequency enhancement, and improved efficiency. Finally, resource utilization and operating performance of the proposed fused CSD FP model are compared with competing FPGA implementation.

The Fast Fourier Transform (FFT)− processor can be described as the most important Numerical Algorithm of our lifetime. In this paper, we have presented different Memory-based Real Fast Fourier Transform (RFFT) Architectures for low-area applications with the Processing Elements (PE) like High Radix Small Butterfly (HRSB), Urdhva Tiryakbhayam Butterfly (UTB) and a PE with vedic multiplier-carry lookahead units are utilized to reduce the Area, Delay and Area-Delay-Product (ADP). In this, the FFT processor is based on Radix-2 Decimation-In-Frequency (DIF) Algorithm, and it also supports higher radix algorithms. The architectures are implemented on various Xilinx Field Programmable Gate Array (FPGA) devices and also on 180 nm Application-Specific Integrated Circuit (ASIC) to compare different parameters like Area, Delay and Power.

To design a residue number system using moduli set \(2^n-1,2^n,2^n+1\). The modulo \(2^n+1\) is the biggest hindrance as it requires (\(n+1\)) number of bits for their representation, while the other two sets use only n bits. In this paper, we present a new algorithm to design radix-8 modulo \(2^n+1\) multiplier using a modified weighted method with light bias. The multiplier uses only \(\lfloor n/3 \rfloor +2\) modulo reduced partial product along with bias term. The new multiplier is also capable to handle zero input. The proposed design is compared with recently proposed technique, and the synthesis result shows 27.14–38.56% less power consumption with almost same area.

This paper presents the comparative analysis of partial product generators (PPG) for decimal multiplication using signed digit (SD) radix-10, radix-5 and radix-4 encoding schemes. PPG is the first step in obtaining the multiplication of two given numbers. For recoding of the BCD numbers, we have used 4221, 5211 and 5421 redundant BCD codes. The performance is compared based on the synthesis results obtained. Verilog is used as the hardware description language for the design. Synthesis and simulation is performed using Xilinx Vivado 2016.1.

This chapter presents split-radix FFT algorithms. First, split-radix FFT algorithm is given. Next, extended split-radix FFT algorithm is described.

This work presents new flexible-architecture for maximum-a-posteriori (MAP) decoder with multi-radix modes to support various throughputs at different levels of power consumption. We have designed major internal blocks of MAP decoder using extensive steering logic to support radix-2/4/8 operating modes. These designs enable efficient clock-gating of our decoder for low-power consumption in different operating modes. This decoder-architecture is post-layout simulated in 65 nm-CMOS process and its performance analysis showed that the bit-error-rate (BER) of 10\(^{-4}\) could be achieved at 5 dB. Implementation result shows that the suggested MAP decoder could achieve throughput in the range 270−810 Mbps with the corresponding power consumption range of 12.24−37.67 mW. In comparison to the state-of-the-art, our design achieved 38% higher throughput and 61% lower power consumption.

Digital signal processor (DSP) is widely used in wireless communications to compute fast Fourier transform (FFT) or its inverse (IFFT). This paper presents the butterfly unit (BU) suitable for DSP to compute FFT/IFFT. The dynamic range of input sequence is increased by representing them using 16-bit floating format. The BU performs trivial addition as well as complex multiplication in a single cycle. The proposed BU is free from multiple processing elements. This BU also eliminates the rounding of twiddle coefficients occurred in fixed-point data representation and reduces the error.

A fast squaring technique for the operands nearer to a particular radix is reported in this paper. The technique offers significantly less computational complexity which reduces the processing time to a large extent. Considering the applicability of the technique for a particular set of numbers which are in the vicinity of the corresponding radix, it is shown that the technique is equally acceptable for very large radix number. The proposed approach has been verified using Xilinx ISE Vertex-7 FPGA device. Simulated findings showed that with a significant increment in radix value (99.87%), the change of propagation delay is extremely small (2.33%), and corresponding increase in power dissipation is within tolerable range (29.84%). The results show the improvement in speed and computational complexity.

In this paper, an efficient synthesis technique for high-speed multivalued ALU for \((2^{p} \pm q)\) radix system is proposed with reduced complexity. Addition, subtraction, increment/decrement and basic logical operations are implemented just by rotation of the matrix or shifting of a few elements, and thus minimum number of computational steps is involved; which saves CPU time usage. Matrix representation for all the operations is provided in a tabular manner with pseudocode for the proposed \((2^{p} \pm q)\) radix system in order to understand the detailed procedure of operations. All the pseudocodes have been verified using Xilinx ISE 14.1 simulator using Vertex-7 XC7VX330t device. Lower computation time and complexity make the ALU efficient than those already proposed in the available literature.

This paper introduces high-performance pipelined 256-point FFT processor based on Radix-22 for OFDM communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm. Radix-2 butterfly’s complexity is very low and Radix-22 CFA algorithm reduces number of twiddle factors compared to Radix-4 and Radix-2. The proposed design is implemented in VHDL language, synthesized using XST of Xilinx ISE 14.1, and simulated using ModelSim PE Student Edition 10.4a successfully. Also, MATLAB code has been written and simulated with MATLAB R2012a tool. The computation speed of proposed design is observed to be 129.214 MHz after the synthesis process and SQNR is 50.95 dB.

This paper presents design of asynchronous parallel adder by using recursive approach and comparison of various parameters such as average power, power-delay product, and number of transistors to design different adders. The parallel asynchronous self-timed adder designed using half adder along 2:1 multiplexer requires minimum interconnection. These adders have propensity to run faster than existing adders for random data. Parallel adder based on radix method provides faster computation of sum and reduces delay which is generated by carry chain. One-bit asynchronous parallel adder is designed with 24T transistor, while 1-bit radix adder is designed with 28T. In radix-based parallel adder, firstly carry is generated and then generated carry is used in sum propagation, which provides low area. Both adders are implemented using Mentor Graphics tool on tsmc018.mod process.