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High quality interpoly dielectrics are required for non-volatile memories (NVM) in order to achieve long term data retention and endurance over many program/erase cycles. LPCVD high temperature oxide (HTO) deposited at 800°C-900°C is investigated for use in oxide-nitride-oxide (ONO) interpoly dielectric stacks. HTO allows for reduced thermal budgets, improved conformal coverage at edge features and more flexibility in scaling the ONO stack compared to thermal oxide layers. SIMS and atomic force microscopy results indicate that smooth, high quality films are deposited with a rms roughness of 0.12nm. Etch rates of as-deposited films are lowered 35% following several densification anneals. Field strengths (at 1μA) of 7-8MV/cm and leakage currents in the pA range are measured. Centroid measurements on sressed oxides show traps to be located at the HTO/polysilicon interfaces. Finally, double poly flash memory cells fabricated with ONO stacks containing HTO top oxide show improved field strength and data retention.

Gate dielectrics for advanced ULSI circuits are rapidly scaling below 10 nm. Thinner dielectrics and smaller lateral dimensions are essential to produce high performance transistors for memories, microprocessors and microcontrollers. In this overview we will discuss the factors that affect the performance and reliability of scaled gate dielectrics. Process parameters that affect oxide and oxynitride dielectrics include substrates, pre-gate cleaning, growth parameters and growth techniques as well as oxide and oxynitride dielectric materials. Thin dielectrics require new or modified measurement methods and extensive use of physical analysis techniques such as SIMS, XPS, AFM and TEM to characterize these materials. Boron diffusion through thin gate oxides, HCI stress, and process induced damage can degrade dielectric quality and affect long term reliability. These factors will affect the performance and reliability of circuits with scaled gate dielectrics.

The nucleation and growth of in situ doped, LPCVD silicon films was analyzed using atomic force microscopy, variable-angle spectroscopie ellipsometry, and transmission electron microscopy. The RMS surface roughness initially increases from 0.5 to 5.7 nm with increasing deposition times and then rapidly decreases to 0.5 nm for longer times. Ellipsometry data was modeled using two layers where the top layer consists of a mixture of amorphous Si plus voids and the bottom layer is a continuous amorphous Si layer. Cross-section TEM reveals the nuclei size and structure for these silicon films and confirms the results of the other techniques.

We have characterized the surface topography of silicon films from different deposition and doping process sequences using AFM and optical reflectivity. The resulting surface structures after deposition, doping, oxide growth, and oxide removal correlate with the electrical leakage currents and breakdown voltages of double polysilicon capacitors. As-deposited amorphous films had smoother surfaces than those deposited in the crystalline state. Gas-phase diffusion doping increases the surface roughness. Only the amorphous in situ doped films retained a smooth surface following oxidation, yielding low leakage capacitors with breakdown fields above 8 MV/cm. Surprisingly, implanted amorphous films exhibited the roughest interfaces, resulting in lower breakdown fields. This study has shown that AFM provides an effective, quick, non-destructive diagnostic technique for semiconductor processing.

Rapid thermal annealing (RTA) technology offers potential advantages for GaAs MESFET device technology such as reducing dopant diffusion and minimizing the redistribution of background impurities. LEC semi-insulating GaAs substrates were implanted with Si at energies from 100 to 400 keV to doses from 1 × 1012 to 1 × 1014/cm2. The wafers were encapsulated with Si3N4 and then annealed at temperatures from 850-1000° C in a commercial RTA system. Wafers were also annealed using a conventional furnace cycle at 850° C to provide a comparison with the RTA wafers. These implanted layers were evaluated using capacitance-voltage and Hall effect measurements. In addition, FET’s were fabricated using selective implants that were annealed with either RTA or furnace cycles. The effects of anneal temperature and anneal time were determined. For a dose of 4 × 1012/cm2 at 150 keV with anneal times of 5 seconds at 850, 900, 950 and 1000° C the activation steadily increased in the peak of the implant with overlapping profiles in the tail of the profiles, showing that no significant diffusion occurs. In addition, the same activation could be obtained by adjusting the anneal times. A plot of the equivalent anneal times versus 1/T gives an activation energy of 2.3 eV. At a higher dose of 3 × 1013 an activation energy of 1.7 eV was obtained. For a dose of 4 × 1012 at 150 keV both the RTA and furnace annealing give similar activations with mobilities between 4700 and 5000 cm2/V-s. Mobilities decrease to 4000 at a dose of 1 × 1013 and to 2500 cm2/V-s at 1 × 1014/cm2. At doses above 1 × 1013 the RTA cycles gave better activation than furnace annealed wafers. The MESFET parameters for both RTA and furnace annealed wafers were nearly identical. The average gain and noise figure at 8 GHz were 7.5 and 2.0, respectively, for packaged die from either RTA or furnace annealed materials.

Polysilicon films were deposited on the following four dielectric layers: 0.10 μm Si02, 0.10 μm Si3N4, 1.0 μm Si02 and a dual layer of 0.10 μm Si3N4 over 1.0 μm Si02. The films were doped with As or P and then annealed with a scanning CW-argon laser. The resulting sheet resistance at a given laser power depends upon both the dielectric material and its thickness. The threshold power, that causes complete melting of the polysilicon, is inversely proportional to the thermal resistance of the underlying dielectric layers. With certain laser parameters and substrate film combinations, excessive thermal stresses cause cracking of the polysilicon films. The laser annealing process is also influenced by the net optical reflectance of the polysilicon/ dielectric multilayer films.

The purpose of this study is to analyze ion implant damage profile using RBS and ellipsometry. Silicon wafers were implanted with 75As at 100, 200 or 300 keV; doses were chosen to generate constant peak impurity concentrations at each energy. The samples were then analyzed using RBS to obtain damage- depth profiles and ellipsometry to obtain Δ,ψ parameters. At light doses decreasingΔ values correspond to increased scattering yield; at higher doses ψ increases rapidly as the scattering yield approaches the random value. The higher energy implants shift the Δ-ψ curves to larger ψ values. Multilayer structures, that include lightly damaged silicon on either side of the project range as well as more damaged near the projected range, are required to model the ellipsometer parameters.

Five different RTP units have been examined. These are the Varian RTP-800, the Eaton ROA-400, the A.G. Associates 2101/2106, the Tamarack 180A-C and the Varian IA-200. Each system is a cassette-to-cassette serial processor designed for use in a high volume semiconductor fabrication line. These units will heat a wafer from room temperature to 400–1400C in times on the order of a few seconds. Each unit uses radiation to heat and cool the wafer. The different radiation sources, wafer handling systems, temperature measurements and control computers are discussed. The control of slip and nonuniform temperatures is presented as well as information regarding the types of ambients that can be used in each system.

Electrical measurements and Rutherford backscattering have been used to evaluate the thermal stability of single crystal and polycrystalline Si films that were ion implanted and laser annealed. The films were implanted with 75As or 31p and annealed with either a pulsed ruby, a pulsed Nd:YAG or a CW­Ar+ laser. The samples were then thermally annealed at temperatures between 450 and 900°C. The single crystal samples implanted with arsenic below 1 × 10-15 cm−2 were thermally stable. For higher doses the electrical concentration reaches a minimum at 800°C. The same trends are observed in the polysilicon films for sufficiently high doping levels. RBS shows that As is precipitating at 700°C in single crystal material and has begun to go back into solution at 900°C for concentrations of ∼7 × 1020 cm−3. Similar trends are observed for 31P implanted samples.

Polycrystalline silicon films of 300 nm thickness were deposited on oxidized wafer surfaces, implanted with As, and annealed on a Varian IA 200 rapid thermal annealer. Transmission electron microscopy was used to study through-thickness and cross sectional views of grain size and morphology of as-deposited and of transient annealed films. A bimoda] distribution of grain sizes was present in as-deposited polycrystalline silicon films. The first population was due to columnar growth of some grains to a final average diameter of 20 rm. The second population of small equiaxed grains of 5 nm average diameter were formed early in the deposition process. During transient annealing grains in the first population grew rapidly up to 280-nm equiaxed grains. After this the growth rate decreased due to the grain size reaching the thickness of the film. Grains in the second population grew rapidly up to a size of 150 nm, after which the growth rate was lowered due to grains impinging upon one another. The grain growth processes for both populations have been described with a modified model for interfacially driven grain growth. This model accounts for diffusion and grain growth which occur with rapidly rising and falling temperatures during short annealing times characteristic of transient annealing processes.

Ohmic contacts to GaAs have been studied using a high resolution TEM, an SEM and a STEM with an energy dispersive x-ray attachment. Two different deposition sequences of the constituent Au-Ge-Ni metals yielded specific contact resistivities that varied by one order of magnitude. Crosssection images of the interface between the GaAs and the metal Au-Ge-Ni layers following alloying showed protrusions at the interface. Contacts with low specific resistivities showed deeper protrusion and also significantly more Ge and Ni in the GaAs.

Rapid thermal annealing (RTA) technology offers potential advantages for the processing of ion implanted GaAs. High energy implants of 300 keV or above are used for power MESFETs as well as in the ohmic contacts for low noise devices. The purpose of this paper is to investigate and characterize the RTA of Si implants into LEC GaAs using implant energies of 300keV and above, and a range of doses from 2.3 ×1012 to 3×1014 /cm2. The wafers were analyzed using capacitance-voltage and Hall measurements. Factors which cause variability in pinchoff voltage are identified and an RTA process comparable to conventional furnace annealing is presented for low dose implants. Superior implant activation is observed for higher dose implants through the use of higher annealing temperature.

Polycrystalline silicon films were transient preannealed, As implanted, and transient post-annealed at peak temperatures up to 1250°C for times up to 17.5 seconds. Structural changes occurring during post-annealing were examined by transmission electron microscopy. These results were correlated to Rutherford Backscattering and sheet resistance results. The grain size, which increased from 5–20 to 150–300 nm during preannealing, did not increase during post-annealing. During early stages of post-annealing, As diffused along grain boundaries and generated dislocation sources at grain boundary surfaces. Subsequently, as annealing progressed, a fine, As-rich cellular network structure propagated into the grains until the structure of an entire grain was transformed into a fine cellular network at the longest annealing times. Residual stresses in the film were relieved during formation of the network structure. The sheet resistance of preannealed samples, in comparison with non-preannealed samples with similar implantation and final transient anneals, was lower at shorter annealing times due to the larger grain size, which increased mobility, and the reduced grain boundary area, which trapped less As. It was also lower at longer annealing times due to the formation of the cellular network structure. In subsequent furnace stability tests for 30 minutes at 700–900°C, the sheet resistance increased less for preannealed than for non-preannealed samples.