Search

A theoretical model based on two-body contact theory is established to simulate the contact pressure distribution arising from wafer curvature which is caused by film stress during CMP process. Both wafer and pad deformations during the contact process are considered. The profiles of the contact pressure distribution for wafers with different curvature radius are simulated. The influences of wafer curvature on mean removal rate and within wafer removal rate nonuniformity (WIWNU) are simulated and compared with the experimental data. According to the two-body contact model, when the pad is in contact completely with the wafer, the profile of the contact pressure has almost the same trend whether the wafer has an upward or a downward curvature. The mean value of the contact pressure will increase with increasing of radius of downward curvature. WIWNU will decrease with increasing pre-polish wafer bow from concave (upward curvature) to convex (downward curvature). The results from the simulation correlated with the experimental data and demonstrated the validity of the model. The results are helpful for controlling and reducing the wafer to wafer removal rate nonuniformity and within wafer removal rate nonuniformity in CMP.

Coherent Gradient Sensing (CGS) is a full-field optical technique that produces real-time images of macroscopic wafer curvature, which, for thin films, can be related to stress through Stoney's equation. Here we describe the use of CGS as an in situ diagnostic to observe film stress distributions during chemical vapor deposition. The application of this method to measure oxygen diffusion rates in thin film YBa2Cu3O6+δ(YBCO) and stresses in thin film PbxBa1-xTiO3 (PBT) under chemical vapor deposition (CVD) conditions will be discussed.

Uncracked HVPE-GaN layers of different thicknesses were investigated using high resolution x-ray diffraction at variable temperatures. The absolute lattice parameters as well as the wafer curvature were measured simultaneously at different temperatures. All samples were found to be under biaxial tension at growth temperature. At room temperature the GaN film is under biaxial compression while the substrate is tensile strained. A simulation of the stress and curvature of the heterostructures was performed for different thicknesses of the films and substrates and a good agreement was found with the experimentally determined values.

The present work uses wafer curvature (disk) method to measure the temperature variation of the biaxial modulus and the thermal expansion coefficient TEC from 25°C to 205°C. The following thin films were measured: PolySi, low stress LPCVD SixNy and (Ba0.7, Sr0.3)TiO3 (BST). To improve the precision, perfect circular thin wafers were used: 4 inches circular 280μm thick Si and 450μm thick Fused Silica. The measurements were performed using a commercial Tencor FLX2320 Stress Measurement System. The film thickness was measured with Tencor TF1 thin film optical system.

Using Si and GaAs substrates, the coefficient of thermal expansion (CTE) and the bi-axial modulus of thin hydrogen silsesquioxanes (HSQ) films are deduced by means of wafer curvature measurement. The same properties of plasma-enhanced CVD oxide are also reported.

A new method is presented for the measurement of the radii of curvature R of semiconductor wafers using the magic-mirror (Makyoh) technique. A flat mirror is placed beneath the sample, thus a second, “contour” image of the sample is formed beside the Makyoh image. From the ratio of the two image sizes, R can be determined using a set of reference curved mirrors. Model calculations show good agreement with the results. Other examples of assessing of the flatness of semiconductor samples are presented as well.

Stress evolution was studied during growth of Cu/Pd multilayers using an in-situ, laserbased wafer curvature technique which allowed measurement of stress changes associated with sub-monolayer thickness increases. The apparent stress in the Cu layers changes during growth, from compressive, for thickness less than about 0.5 nm, to tensile for thicknesses above this. The stress behavior in the Pd layers depends on the thickness of the underlying Cu layer. Pd deposited on thick (2 nm) Cu layers is under an apparent compressive stress, while Pd deposited on thin (< 1 nm) Cu layers is initially under a tensile stress but changes to a compressive stress at about 0.5 nm. The overall compressive stress maxima observed in multilayers at a bilayer period of 2 nm is explained by this in-situ behavior. The stress behavior in this system is consistent with either island growth of Cu, or thickness dependent alloying behavior, or both.

We describe a technique for measuring thin film stress using wafer curvature that is robust, compact, easy to setup, and sufficiently sensitive to serve as a routine diagnostic of semiconductor epilayer strain in real time during MBE or CVD growth. We demonstrate, using growth of SiGe alloys on Si, that the critical thickness for misfit dislocation can clearly be resolved, and that the subsequent strain relaxation kinetics during growth or post-growth annealing are readily obtained.

Wafer curvature measurements of a trilayer (SiO2 / AlSiCu / Si) structure are compared to that predicted by a weighted sum of individual measurements of SiO2 and AISiCu films on Si, and significant differences are found to exist for temperatures above 200°C. A straightforward analysis of the stresses in each layer has been modeled using an extension of a model by Feng et al. which assumes uniform plastic deformation throughout the Al. The modeling results suggest a straightforeward method for determining stresses in deformable thin films that are confined by elastic overlayers. A comparison of the stress-temperature behavior for unpassivated and passivated AISiCu films reveals that the confined films exhibit less plastic deformation and both higher tension and compression during thermal cycling.

The tetragonal distortion present in both VPE and LPE In1-xGaxAs was measured from X-ray rocking curves of the (511) reflection. These measurements were then used to establish coherency limits. In addition, wafer curvature was measured and compared to that calculated via an expression which incorporates both tetragonal distortion and misfit dislocations. Agreement was found except for a case in which stacking faults were present.