Search

In this work, we study the Transient Liquid Phase Bonding (TLPB) for flip chip interconnexion using copper pillar and SnAg solder alloy technologies. Cu and SnAg bumps with a size of 90 × 90 µm2 were deposited using electroplating process with a thickness of 20 µm and 15–30 µm, respectively. Two types of Cu were deposited: with or without additives. Before the TLPB process, soldering experiments with or without pre-reflow were carried out at 250 °C in order to insure a good filling of the joint. Afterwards, isothermal holdings up to 4 h were performed in the temperature range between 250 and 350 °C under air atmosphere. Two main aspects of Cu/SnAg system are studied and analyzed: (i) the evolution of morphology, microstructure, and growth kinetics of intermetallics (IMCs) during the TLPB and especially (ii) the formation and growth of gas bubbles within the liquid solder during TLPB process. Destructive (scanning electron microscopy) and non-destructive (X-ray) characterizations are performed to analyze and understand the evolution of microstructure as well as the formation and evolution of cavities within the joint during the TLPB process. Non-destructive X-ray radiography with 5 µm resolution and 3D X-ray tomography analysis with 0.7 µm resolution were conducted for the same joint at different steps of its evolution between its initial state (just after the soldering process: about 3 min at 250 °C) and 4 h at 250 °C in order to follow “in situ” the evolution of volume defects inside the joint and especially the evolution of gas bubbles within the joints.

The low-k/ultra-low-k (LK/ULK) dielectric materials are incorporated in the 40 nm technology node and beyond to reduce resistance and capacitance (RC) delays and improve chip performances. However, the LK/ULK integrity becomes critical in a flip-chip process because of the LK/ULK materials' higher porosity and fragility in mechanics. In this paper, we proposed a three-dimensional (3D) one-level global/local finite element model to study stresses and fracture behaviors in the chip with ULK dielectrics in the heating flip-chip process using SIMULIA ABAQUS software. The global model includes an effective thin layer that is equivalent to Cu/low-k multilayer interconnections. On the basis of stress analysis, the precracks at different locations of back-end of line (BEOL) were introduced to estimate the values of energy release rate (ERR) along the 3D crack fronts and the possible crack extension was discussed. Furthermore, the ERR affected by the ULK modulus, polyimide thickness and copper pillar diameter was investigated. The analysis reveals that the values of ERR are higher in upper layers of the BEOL and their values at interfaces of Cu/ULK are as much as two times than in ULK. The ERR reaches its maximum value under the edge of copper pillar with higher first principal stresses. The crack propagation becomes critical due to a quickly rising value of ERR when the polyimide (PI) thickness or the diameter of copper pillar is decreased. The study helps to understand the fracture behaviors in BEOL of an advanced chip during a packaging process.

Thermal compression bonding (TCB) has been widely used in flip chip bonding processes for three-dimensional integrated packaging. Therefore, studying the TCB process and solder joint structure is significant for improving reliability. In this study, a Ni layer was deposited between the Cu/Sn-3.5Ag solder bumps of upper and lower chips, and TCB process tests were carried out at different bonding temperatures, forces and times. The solder height at the top and bottom of the copper pillar were recorded. Through the establishment of a mathematical analysis model, the relationship between the solder joint height and maximum stress was analyzed theoretically, and the trend of the shear stress and solder joint height was obtained from die shear tests. Then, the solder joint morphology, strength and microstructure composition of the microbumps were observed after aging. Our results showed that the growth rate of intermetallic compounds (IMCs) for Cu/Sn-3.5Ag microbumps with a 25 μm diameter was 2.5 times those with a 100 μm diameter and that the Ni barrier layer prevented the diffusion of Cu in Sn-3.5Ag solder. In addition, the Ni layer improved the strength of the Cu/Sn-3.5Ag joints after aging. Finally, with extended aging time, the fracture site was found to move from the solder region to the Cu6Sn5 layer for the Cu/Sn-3.5Ag samples, while it remained at the Sn-3.5Ag/IMC interface for the Cu/Ni/Sn-3.5Ag samples.

Open-cell metal foams suffer from severe deterioration in mechanical properties due to their enriched three-dimensional interconnected holes. In this paper, reinforcing copper pillar(s) or tube(s) are embedded into the foam matrix to form “composite” structure to enhance the open-cell copper foams. To do this, a simple positioning device is designed for preparation of the green porous copper aligned with directional through hole(s) based on a tapping method. Then the reinforcing pillar(s) or tube(s) are inserted into the hole(s) and sintered together. By this means, the mechanical properties of the copper foams are significantly improved. The energy absorption capacity of the composite foams has also been improved because of a higher and wider yield platform compared with the unreinforced copper foams.

The finite element software ANSYS was used to simulate the solder joints in the flip chip, and the stress and strain distribution results of the solder joints are displayed. During the simulation process, the final results of the simulation were not the same when the solder joints of different sizes were used. The simulation results under thermal cycling load show that the area where the maximum stress and strain occur is mostly distributed in the contact area between the solder joint and the copper pillar and at the solder joint. During the entire thermal cycling load process, the area where the maximum change in stress and strain occurs is always at the solder joint, and when the temperature changes, the temperature at the solder joint changes significantly. From the comprehensive analysis, the relevant empirical correction calculation equation is used to calculate and predict the thermal fatigue life of the solder joint. We found that when the diameter of the solder joint is constant, the increase in the height of the weld point will increase its thermal fatigue life; when the height of the weld point is constant, the increase in the diameter of the weld point increases its thermal fatigue life. The effect of height is greater than the effect of diameter.

A new kind of intermetallic compounds (IMC) were found around copper pillar in micron level bumps. To investigate the formation mechanism, three different sized Sn/Ni/Cu bumps (10 μm, 20 μm, 50 μm) were electroplated then reflowed at 230 °C for 100 s. After reflow process, a thin layer of IMC was formed around copper pillar, which is attributed to surface wetting behavior. After aging at 170 °C and 200 °C for different times, the growth mechanism of sidewall IMC was observed by scanning electron microscopy combined with electron backscatter diffraction (EBSD) technology. Surface diffusion was considered to be the main driving force for sidewall IMC growth for the activation energy of them was found to be much smaller than that in previous studies. The EBSD results showed a preferred orientation of sidewall Cu3Sn grains being perpendicular to copper periphery, which indicated direction of Cu atoms flux during Cu3Sn growth. Formation mechanism of this novel sidewall IMC was proposed based on surface wetting and surface diffusion. The findings contribute to the failure mechanism study in small size bumps and provide insights into the reliability of 3D electronic packaging.

The low-k/ultralow-k (LK/ULK) dielectric materials are introduced in the back-end of line (BEOL) to reduce the R-C delay in a chip with 40 nm technology node and beyond. The chips are generally packaged using a flip-chip technology, in which copper pillars are electrical connections and mechanical supports. Owing to the thermal mismatch between materials, copper pillars are sheared and higher stresses arise near the roots of the copper pillars, which causes cracks in LK/ULK materials that are porous and fragile in mechanics. In this study a rapid mechanical shear test of a copper pillar was proposed to mimic the corresponding shear force due to a temperature drop by finite element analysis (FEA) and bump shear experiments. FEA results for shear tests are in compliance with that of experiments and the high stress regions are conformed to the failure locations in the BEOL. Using the verified finite element models, a linear relationship between the shear force, the shear height and the temperature differential was built by keeping a bump in a same shear impact, which is valid for the temperature differential within 120 °C. In the suitable temperature range a mechanical shear test can quickly assess the failure possibility of LK/ULK materials caused by a temperature differential for evaluating their reliability in BEOL of an advanced chip.

Copper pillar micro bump is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking and high-density electronic components. In this study, Cu–Cu direct thermo-compression bonding (TCB) and anisotropic conductive paste (ACP) bonding methods are proposed for O 100 µm Cu-pillar bumped flip-chips. The process parameters including bonding temperature, bonding pressure and time are verified by die shear test and SEM/EDX cross-sectional analysis. The optimal bonding condition for TCB with regards to bonding pressure was defined to be 0.5N/bump at 300 °C or 0.3N/bump at 360 °C. In the case of ACP bonding, the minimum bonding pressure was about 0.3N/bump for gaining a seamless bonding interface.

Electroless Ni/electroless Pd/immersion Au (ENEPIG) constitutes a promising metallization to replace the conventional ENIG or Ni/Au for 3D IC integrated module and optoelectronic packaging. Different ENEPIG plating thicknesses with copper pillar solder joints are subjected to thermal aging at 150 °C to investigate the intermetallic compounds (IMCs) formation and growth. Due to low temperature solid-state bonding, both Pd and Au layers do not completely diffused into Sn matrix and participated in the interfacial reactions to form (Pd,Au)Sn4 IMCs phase. (Pd,Au)Sn4 IMCs based on PdSn4 phase with dissolved Au, exhibits high growth rate and substantial consumption of Sn from solder. Upon increasing the aging time, it is found that (Cu,Ni)6Sn5 IMCs and (Pd,Cu,Au)Sn4 phase form at interface and follows a diffusion control mechanism, which weakened the solder joint and caused brittle fracture in a die peel test. (Cu,Ni)6Sn5 IMCs growth rate increases with decreases Pd thickness. Therefore, the types of IMCs formation, growth rate, and reliability of Cu pillar joint strongly depend on bonding temperature, Au and Pd thicknesses, and solder volume. Based on this study, the authors recommend suitable ranges of Au and Pd layer thicknesses for reliable Cu pillar solder joints.

Although the copper (Cu) pillar bump (CPB) was developed in accordance with recent trends of miniaturized, multifunctional, and high-performance technology, its thermomechanical reliability remains in question. Accordingly, a hole was drilled into a CPB to increase its thermomechanical reliability, and the viscoplasticity behaviors of the two structures were subsequently compared through finite element analysis. In particular, this study applied the Anand model, which addresses both plastic strain and creep strain, as well as a submodeling technique to increase the accuracy of the analysis and decrease the analysis time. In addition, this study confirmed the superiority of the thermomechanical reliability of drilled Cu pillar bump through a hysteresis loop, which showed the equivalent stress versus equivalent inelastic strain of the solder joint interfaces. Moreover, the study compared the inelastic strain energy density values. The results demonstrated that the drilled copper pillar bump does indeed have a smaller inelastic range and a lower inelastic strain energy density.

Cu pillar samples were subject to the thermal cycling test along with current stressing to investigate its reliability issues under the coupling effect. Analysis of scanning electron microscopy (SEM) pictures of Cu pillar bumps showed the evolution of interfacial microstructure. The finite element analysis pointed out the probable site of cracks initiation based on the strain and stress distribution. Three failure modes, electromigration (EM) induced cracks at Cu6Sn5/Sn interface on cathode, cracking of Cu/Cu3Sn interface on anode side, and fatigue-creep induced cracks in Sn solder, took place at the interfaces of copper pillar interconnect under electric current and thermal cycling. In addition, EM induced failure increased while fatigue-creep failure decreased with electric current density. The failure mechanisms were analyzed from stress concentration, interfacial morphology and voids formation respects.

Considering the current induced voids flow will accelerate the creep strain rate and lower the strength of the solder, a current induced activation energy change, ΔQe is added in the Anand model. A lifetime prediction model was constructed based on linear damage rule for the current-thermal cycling coupling test. To verify the accuracy of the model, mean-time-to-failure (MTTF) of copper pillar has been experimentally and analytically investigated under the combination of thermal cycling with temperature range of −40 to 125 °C and a superimposed electric current with current densities of 17.4–22.4 × 104 A/cm2. The experimental results reveal that the MTTF sharply decreases with the increasing current density. The acceleration factors are calculated, which is consistent well with the prediction model.

The flip chip process involves the deposition of solder bumps on the chip surface and their subsequent direct attachment and connection to a substrate. Underfilling traditional flip chip packaging is typically performed following a two-step approach. The first step uses capillary force to fill the gap between the chip and the substrate, and the second step uses epoxy molding compound (EMC) to overmold the package. Unlike traditional flip chip packaging, the molded underfill (MUF) concept uses a single-step approach to simultaneously achieve both underfill and overmold. MUF is a simpler and faster process. In this study, a 2D numerical model is developed to simulate the front movement of EMC flow and the void formation for different geometric parameters. The 2D model simplifies the procedures of geometric modeling and reduces the modeling time for the MUF simulation. Experiments are conducted to verify the prediction results of the model. The effect on void formation for different geometric parameters is investigated using a 2D model.

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captured deformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.

Flip chip technology is an attractive choice for high-density packaging and complex microsystem architectures. A critical element in the successful application of flip chip technology is the reliability of solder bumps. In this paper a nondestructive detection method is presented for the flip-chip solder bump inspection using ultrasonic excitation and vibration analysis. Simulations are implemented to explore the feasibility of this method, and experimental investigations are also performed, where the flip chips are excited by continuous ultrasonic waves and their vibration velocities are measured by a laser scanning vibrometer for further analysis. The results reveal that the defective chips can be distinguished from the good chips by the chip vibration velocities with the feature coefficient α, which proves the effectiveness of this method. Therefore, it may provide a new path for the improvement and innovation of flip chip on-line inspection systems.

In present study, a backside-etched silicon chip with a polysilicon diaphragm flip-chip attached on a printed wiring board (PWB) and globally bumped on a FR4 substrate was investigated based on finite element analysis (FEA) for determining three key parameters of flip chip chip size packaging (FC-CSP), namely, the size of solder bump, the thickness of PWB substrate, with/without U8437-3 underfill. In order to improve the reliability and the yield of MEMS packaging, the thermal cycle of environmental test ranging from −40° to 125° was utilized for determination of the influence of key parameters on the thermal-induced stresses and the deflection in the diaphragm as well as the warp of PWB substrate. In addition, the thermal stress occurred at the interface between solder bump and silicon chip was also analyzed to understand the failure mechanism of solder bump. According to the simulation results, we concluded three phenomena as follow: (1) As the thickness of substrate increased, the thermally-induced stress in the diaphragm also increased, but the deflections of diaphragm and substrate decreased instead. (2) As the size of solder bump increased, both of stress and deflection in the diaphragm decreased, however, the warp of substrate was insensitive to the size of solder bump. (3) If the underfill material encapsulated the solder bump between chip and substrate, the induced stress occurred at the interface between solder joint and chip was decreased, however, the stress in the diaphragm was increased instead. On the other hand, the deflection was smaller in the diaphragm but larger in the substrate as the underfill existed in the model. In general, the parametric study can provide the basis for the flip chip package of MEMS device with diaphragm, such as MEMS microphone, MEMS pressure sensor, etc.

We have developed a microphone package using flip chip technology instead of chip and wire bonding to create smaller MEMS microphones. With this new packaging technology the transducer chip and an ASIC chip are flip chip bonded on a ceramic substrate. The package is sealed by a polymer foil laminated over the chips and by a metal layer. The sound port is on the bottom side in the ceramic substrate. In this paper the packaging technology is explained in detail and results of electro-acoustic characterization and reliability testing are presented. We will also explain the way which has led us from the packaging of Surface Acoustic Wave (SAW) components to the packaging of MEMS microphones.

In this study, we fabricated eutectic Au–Sn (Au–20 wt% Sn) flip-chip solder bumps from a single electroplating bath. After reflowing, the average diameter of the solder bump was approximately 80 μm. The (Ni,Au)3Sn2 phase was initially formed when the liquid Au–Sn solder reacted with the Ni UBM (under bump metallization). After aging at 150 °C, the (Ni,Au)3Sn2 intermetallic compound (IMC), which formed at the interface during reflow, was fully transformed into the (Au,Ni)Sn IMC due to the restricted supply of Ni atoms from the UBM to the interface. On the other hand, after aging at 250 °C for 1000 h, two IMC layers, (Au,Ni)Sn and (Ni,Au)3Sn2, were formed at the interface. The lower (Ni,Au)3Sn2 phase was formed when the (Au,Ni)Sn phase reacted with the Ni UBM. The interfacial (Au,Ni)Sn IMC grew with the preferential consumption of the available δ-phase in the solder matrix. Eventually, the ζ-phase covered most of the interfacial layer. In the bump shear tests, the Au–Sn/Ni joint aged at 150 °C fractured through the bulk of the solder, confirming the mechanical reliability of the interface. In contrast, the Au–Sn/Ni joint aged at 250 °C fractured along the interface, thereby demonstrating brittle failure, possibly a result of the brittle IMC layer at the interface.

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.

A variety of Pb-free solder alloys have been proposed for use as interconnects for electronic packaging including Sn−Ag, Sn−Cu, Sn−Ag−Cu, Sn−Ag−Bi, and Sn−Sb, among others. This paper presents a review of the behavior of promising Pb-free solder alloys as related to their microstructure. Recommendations of optimal alloy composition as a function of performance requirements are given. For surface mount applications, eutectic Sn−Ag−Cu is recommended as the optimal alloy. For flip chip interconnects, the eutectic Sn-Cu alloy has the best performance. The materials and process trends of Pb-free packaging are summarized with optimal conditions identified.

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.

The paper presents numerical simulations and experimental investigations of flip chip modules having silicon, alumina ceramics, polyimide or polyester foil, or epoxy glass laminates as substrate material under thermo cycle test conditions. Some of the flip chip modules were stabilised additionally by filling the remaining gap between chip and substrate with an epoxy underfiller. The presented results concern the stress distribution in the joints as basis of their shape optimisation for the modules without underfiller as well as the evaluation of the metallographic cross-sections of the joints before and after the thermo cycles. Both, the simulations and the experiments, lead to the unambiguous result: The flip chip modules can be made reliable enough for industrial application in all cases with the help of the underfiller.

The paper presents new material data of real flip chip solder joints. A testing apparatus was designed to perform reversible shear tests on flip chip joints. In contrast to previous test setups for similar purposes this tester provides an infinite stiffness, a very high precision force (1 mN resolution) and displacement (20 nm resolution) measurement. The experimental program included cyclic shear tests for elastic plastic material data as well as a newly developed reversal creep and relaxation test for time depended material properties. A subsequent FEM simulation was applied to evaluate experimental raw data and to determine the parameters of material models provided by ANSYSTM. A user defined creep model had been added to the source code, in order to receive a convenient solder model for FE-Analysis of SnPb37 flip chip solder joints under thermomechanical stresses in electronic packages. The results of this study shows that the material behavior of flip chip solder joints is much more like that of bulk samples with a comparable micro structure than it is commonly believed up to now, because of the previously published data.

In the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps, highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as l.tm Al/0.2 μm Ti/5 μm Cu, l μm A1/0.2 μm Ti/l μm Cu, 1 μm A1/0.2 μm Ni/1 μm Cu and 1 μm At/10.2μm Pd/l μm Cu, laid under eutectic Pb/Sn solder of low melting point, were investigated with regard to their interfacial reactions and adhesion properties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMC) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1 μm AI/0.2μm Ti/5μm Cu and 1 μm Al/0.2 μm Ni/l μm Cu even after 4 solder reflows or 7 day aging at 150°C. In contrast, l μm Al/0.2 μm Ti/l μm Cu and l μm A1/0.21μm Pd/μm Cu shows poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. Thin 1 μm Cu and 0.2 μm Pd diffusion barrier layer were completely consumed by Cu-Sn and Pd-Sn reaction.

The article discusses the possibility of a computer security breach as a result of a field-programmable gate array microchip vulnerability discovered by researchers, adapted from the "Guest Blog" on the periodical's website blogs.ScientificAmerican.com/guest-blogs as of August 2012.

The flexibility and cost advantages of the wire bumping process are making it increasingly attractive as an alternative bumping method for low I/O flip chip technologies. In this study, electrical measurements from DC to 8.1 GHz and die shear experiments are used to assess the thermo-mechanical integrity of Au/2%Pd wire bumped GaAs/Al2O3 flip chip modules. Finite Element Modeling results for in-process and in-service temperature cycling indicated that the maximum stress of the flip chip module is well below the failure stresses for GaAs, Al2O3 and the Au interconnect. These results are validated by data from thermal cycling experiments. Average shear strength after thermal cycle, thermal shock, and thermal aging (MIL-STD-883C, Condition C) was 64 grams/bump. Electrical characterization (from 45 MHz to 8.1 GHz) using a coplanar waveguide flip chip test structure showed no thermal stress-induced microwave energy losses.