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This research is to design an effective prefetching method required for hybrid main memory systems consisting of dynamic random-access memory (DRAM) and phase-change memory (PCM) components, which can be especially used for big data applications and massive-scale computing environment. Conventional prefetchers perform adequately for regular memory access patterns. However, graph processing applications show extremely irregular memory access characteristics, causing some difficulty in predicting accurate prefetching operation. Therefore, an effective dynamical prefetching algorithm based on the regression method is proposed in this study. We have designed an intelligent prefetch engine that can identify any dynamic accessing characteristics in memory accessing sequences. Specifically, it can select regular, linear, or polynomial regression predictive analysis based on the memory access sequence characteristics, and also dynamically determine the number of pages required for any selected prefetching. We also present a DRAM-PCM hybrid memory structure that can reduce the energy consumption and resolve the thermal issue that hampers conventional DRAM memory systems. Experimental results indicate that the performance can increase by around 40%, compared to that of conventional DRAM memory structures.

This research is to design a history table-based linear analysis method for a DRAM-PCM (phase change memory) hybrid memory system supporting irregular and complex memory accessing patterns in graph processing applications. This linear analysis method can analyze complex memory access patterns in real time through our history table structure, classifying address values requested from the LLC (last-level cache) as the prefetch candidates. Also, the proposed method is to support a prefetching operation from the storage onto the hybrid main memory, causing significant latency losses. Specifically, we proposed a new memory pattern analysis method, which is called a linear analysis based on a history table, to detect any linear memory access patterns from workloads showing irregular accessing characteristics. For the DRAM-PCM hybrid memory, dynamic data that are frequently accessed are stored in the DRAM. Thus, our linear analysis not only categorizes memory access patterns in the form of line patterns but also separates dynamic and static data so that the hybrid memory systems can be managed adaptively and efficiently. Our experiments show that our model can improve performance and energy consumption by 60% and 30%, respectively, compared to those of the traditional DRAM-only memory model. Moreover, our approach can enhance the entire system performance and energy consumption by 11.3%, 6.8%, compared to streamlined prefetcher-based models.

The amount of data is increasing explosively, and many in-memory-based database management systems have been developed to efficiently manage data in real time. However, these in-memory databases mainly use DRAM main memory, which raises problems due to price and energy consumption. To mitigate these problems, we propose a hybrid main memory structure based on DRAM and NAND flash that is cheaper and consumes less energy than DRAM. The proposed system incorporates a prefetching mechanism in last-level cache based on regression analysis to handle irregular memory access from the in-memory application and a migration technique based on clustering between DRAM and NAND flash to mitigate NAND flash slow access latency, which could otherwise significantly degrade system performance. We experimentally confirmed approximately 58% and 51% execution time and energy improvement compared with using DRAM alone. We also compared existing prefetching models without migration to evaluate the proposed prefetching and migration techniques and showed approximately 24% and 23% improvement for execution time and an energy consumption, respectively.

Owing to the exponential growth of real-time data generation, the importance of stream processing is ever increasing. However, the data processing paradigm of stream processing is quite different, so it is difficult to expect high performance from memory systems applied to existing data centers. To solve this problem, two main solutions are suggested in this paper. First, a hybrid main memory and small buffer architecture are designed to reflect the execution characteristics of stream processing. Second, a hardware-based prefetch module supports correlation prefetching. Stream processing tends to accept incoming data in the main memory, so the prefetch module is used to divert data from the main memory layer to the buffer layer based on an intelligent clustering algorithm. This clustering algorithm affects the rapidly changing data access pattern of stream processing applications. By using heterogeneous main memories, not only can one enjoy the fast access latency of DRAM but also its nonvolatility, scalability, and low power consumption. The proposed hybrid memory architecture with our prefetch buffer structure can improve the buffer hit rate by 9–14% over other prefetch methods, reduce energy consumption by 26% over the conventional DRAM-only model, and achieve similar execution time over the 1/8-size DRAM space of the DRAM-only model.

Owing to the increased need for machine learning and artificial intelligence in current cloud computing systems, the amount of data that needs to be processed has exponentially increased. Thus, it is important to optimize memory and storage systems to reduce the energy consumption and execution time of applications. This paper proposes a new Q-learning-based prefetching algorithm for DRAM---NAND flash hybrid main memory architecture. To minimize the computational overheads of learning-based schemes, we have designed two learning policies, namely aggressive learning and lazy learning. The proposed system reduces the energy consumption by about 80% of the memory and storage for Redis, OpenStack Swift which is a cloud computing open source framework and Apache Storm workloads. Further, the overall execution time of workloads in cloud computing applications is reduced by almost half. Using a path generator with a Q-learning-based prefetching algorithm, we realize an increased hit rate of about 21% compared to that with a no-prefetching system, compared to non-prefetching system.

A new storage system that integrates non-volatile with conventional memory, a harmonized memory system (HMS) for object-based cloud storage, is proposed. The system overcomes IO bottlenecks when managing large amounts of metadata and transaction logs and is composed of five modules. The first, the harmonized memory supervisor, is a translation layer for accessing the harmonized array module. It manages address translation, address mapping by page linking, and wear leveling. The second, the harmonized array module, is divided into dynamic and static areas composed of DRAM, and PCM together with NAND flash memory, respectively. The harmonized memory migration engine and data pattern predictor, which anticipates future data flow, are designed to maximize the effectiveness of the PCM array area. The harmonized logging conductor processes the log between the PCM array and NAND flash areas. Experimental results show the total execution time and energy consumption of HMS is 5.77 faster and 4.27 times lower, respectively, than the conventional DRAM-HDD model for object-based storage workloads.

Computational scientific applications tend to be very data I/O intensive, producing a large amount of data as the execution result. In this research, we propose a new storage system using next-generation non-volatile memory that is suitable for exa-scale computing systems. This storage system is called the Cloud Computing Burst System (CCBS) and is composed of a unified table management module, data scoring module, and CCBS storage. In particular, CCBS operates as a workload enlightened storage system using its own data scoring module. The CCBS storage architecture consists of PCM/NAND Flash arrays and a data migration engine. CCBS storage cannot only provide a scaling out feature, but also improve the overall performance of the storage system. In addition, by using new non-volatile memory array, many benefits, such as low energy consumption, density scaling, and high performance, can be achieved. We demonstrate the effectiveness of our proposed system by simulating the storage system using scientific benchmarking tool. Our data scoring algorithm can provide 7% more hit rate than other methods for CCBS. In addition, our proposed system has improved storage system speed by 1.64 times, compared with only NAND Flash conventional model.

This research proposes a phase-change memory (PCM) based main memory system with an effective combination of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.

Next generation non-volatile memory devices are promising replacements for DRAM and Flash memories for mobile devices because of their energy efficiency and non-volatile characteristics. In this paper, we propose a new memory hierarchy system for next-generation non-volatile memory devices that is called an integrated memory-disk (IM-D) structure. It can merge a conventional main memory layer and a disk storage layer into a single memory layer using Phase change memory (PCM) and Flash memories. The IM-D architecture, consisting of a dual buffering IM-D adapter to improve the limited endurance and latencies, an array of PCM/Flash hybrid memories, and an associated memory management module called the IM-D translation layer in the operating system, is designed to utilize the advantages of next-generation non-volatile memory devices and at the same time overcome some shortcomings, like the asymmetric read/write access latencies and limited endurance, of a conventional memory hierarchy system. In the IM-D architecture, we propose an array of PCM/Flash hybrid memories and a migration scheme to enhance the cost effective performance and to reduce access latency. Our experimental results show that the miss rate of the proposed IM-D adapter is reduced by 49 % as compared with the conventional memory module, and the write count is reduced by 60.15 %. In addition, the access latency of the IM-D storage is improved by 45.3 %.