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Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2–5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6–17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM—a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.

Self-Assembly, a process in which molecules, polymers, and particles are driven by local interactions to organize into patterns and functional structures, is being exploited in advancing silicon electronics and in emerging, unconventional electronics. Silicon electronics has relied on lithographic patterning of polymer resists at progressively smaller lengths to scale down device dimensions. Yet, this has become increasingly difficult and costly. Assembly of block copolymers and colloidal nanoparticles allows resolution enhancement and the definition of essential shapes to pattern circuits and memory devices. As we look to a future in which electronics are integrated at large numbers and in new forms for the Internet of Things and wearable and implantable technologies, we also explore a broader material set. Semiconductor nanoparticles and biomolecules are prized for their size-, shape-, and composition-dependent properties and for their solution-based assembly and integration into devices that are enabling unconventional manufacturing and new device functions.

The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.

Ternary content-addressable memory (TCAM) is specialized hardware that can perform in-memory search and pattern matching for data-intensive applications. However, achieving TCAMs with high search capacity, good area efficiency and good energy efficiency remains a challenge. Here, we show that two-transistor–two-resistor (2T2R) transition metal dichalcogenide TCAM (TMD-TCAM) cells can be created by integrating single-layer MoS2 transistors with metal-oxide resistive random-access memories (RRAMs). The MoS2 transistors have very low leakage currents and can program the RRAMs with exceptionally robust current control, enabling the parallel search of very large numbers of data bits. These TCAM cells also exhibit remarkably large resistance ratios (R-ratios) of up to 8.5 × 105 between match and mismatch states. This R-ratio is comparable to that of commercial TCAMs using static random-access memories (SRAMs), with the key advantage that our 2T2R TCAMs use far fewer transistors and have zero standby power due to the non-volatility of RRAMs. By integrating two-dimensional MoS2 transistors with metal-oxide resistive random-access memories, two-transistor–two-resistor ternary content-addressable memory cells can be created, which could be used to search large amounts of data in parallel.

An amendment to this paper has been published and can be accessed via a link at the top of the paper.

Neuromorphic computing systems, which use electronic synapses and neurons, could overcome the energy and throughput limitations of today’s computing architectures. However, electronic devices that can accurately emulate the short- and long-term plasticity learning rules of biological synapses remain limited. Here, we show that multilayer hexagonal boron nitride (h-BN) can be used as a resistive switching medium to fabricate high-performance electronic synapses. The devices can operate in a volatile or non-volatile regime, enabling the emulation of a range of synaptic-like behaviour, including both short- and long-term plasticity. The behaviour results from a resistive switching mechanism in the h-BN stack, based on the generation of boron vacancies that can be filled by metallic ions from the adjacent electrodes. The power consumption in standby and per transition can reach as low as 0.1 fW and 600 pW, respectively, and with switching times reaching less than 10 ns, demonstrating their potential for use in energy-efficient brain-like computing. Vertically structured electronic synapses, which exhibit both short- and long-term plasticity, can be created using layered two-dimensional hexagonal boron nitride.

Photoelectrochemical (PEC) hydrogen production makes possible the direct conversion of solar energy into chemical fuel. In this work, PEC photoanodes consisting of GaAs nanowire (NW) arrays were fabricated, characterized, and then demonstrated for the oxygen evolution reaction (OER). Uniform and periodic GaAs nanowire arrays were grown on a heavily n-doped GaAs substrates by metal–organic chemical vapor deposition selective area growth. The nanowire arrays were characterized using cyclic voltammetry and impedance spectroscopy in a non-aqueous electrochemical system using ferrocene/ferrocenium (Fc/Fc+) as a redox couple, and a maximum oxidation photocurrent of 11.1 mA/cm2 was measured. GaAs NW arrays with a 36 nm layer of nickel oxide (NiO x ) synthesized by atomic layer deposition were then used as photoanodes to drive the OER. In addition to acting as an electrocatalyst, the NiO x layer served to protect the GaAs NWs from oxidative corrosion. Using this strategy, GaAs NW photoanodes were successfully used for the oxygen evolution reaction. This is the first demonstration of GaAs NW arrays for effective OER, and the fabrication and protection strategy developed in this work can be extended to study any other nanostructured semiconductor materials systems for electrochemical solar energy conversion.

Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced.

Carbon nanotube (CNT) thin-film transistor (TFT) is a promising candidate for flexible and wearable electronics. However, it usually suffers from low semiconducting tube purity, low device yield, and the mismatch between p- and n-type TFTs. Here, we report low-voltage and high-performance digital and analog CNT TFT circuits based on high-yield (19.9%) and ultrahigh purity (99.997%) polymer-sorted semiconducting CNTs. Using high-uniformity deposition and pseudo-CMOS design, we demonstrated CNT TFTs with good uniformity and high performance at low operation voltage of 3 V. We tested forty-four 2-µm channel 5-stage ring oscillators on the same flexible substrate (1,056 TFTs). All worked as expected with gate delays of 42.7 ± 13.1 ns. With these high-performance TFTs, we demonstrated 8-stage shift registers running at 50 kHz and the first tunable-gain amplifier with 1,000 gain at 20 kHz. These results show great potentials of using solution-processed CNT TFTs for large-scale flexible electronics., Carbon nanotube thin-film transistor is promising for solution-processed, large-scale flexible electronics, but the device yields remain poor to date. Lei et al. show low-voltage flexible digital and analog circuits based on high-purity and high-yield separation of semiconducting carbon nanotubes.

Carbon nanomaterials have greatly advanced non-volatile memory technology. In this Review, applications of various carbon nanomaterials as memory electrodes, interfacial engineering layers, memory selectors and resistive-switching media are discussed in the context of emerging non-volatile memory devices.

Incredibly thin transistors could deliver even more powerful computers if three research challenges can be solved, argue Ming-Yang Li and colleagues. Incredibly thin transistors could deliver even more powerful computers if three research challenges can be solved, argue Ming-Yang Li and colleagues.

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system., Using chips that mimic the human brain to perform cognitive tasks, namely neuromorphic computing, calls for low power and high efficiency hardware. Here, Yao et al. show on-chip analogue weight storage by integrating non-volatile resistive memory into a CMOS platform and test it in facial recognition.

The Field Effect sensors are broadly used for detecting various target analytes in chemical and biological solutions. We report the conditions under which the pH sensitivity of an Ion Sensitive Field Effect transistor (ISFET) sensor can be significantly enhanced. Our theory and simulations show that by using pH buffer solutions containing counter-ions that are beyond a specific size, the sensor shows significantly higher sensitivity which can exceed the Nernst limit. We validate the theory by measuring the pH response of an extended gate ISFET pH sensor. The consistency and reproducibility of the measurement results have been recorded in hysteresis free and stable operations. Different conditions have been tested to confirm the accuracy and validity of our experiment results such as using different solutions, various oxide dielectrics as the sensing layer and off-the-shelf versus IC fabricated transistors as the basis of the ISFET sensor.

A computer built entirely using transistors based on carbon nanotubes, which is capable of multitasking and emulating instructions from the MIPS instruction set, is enabled by methods that overcome inherent challenges with this new technology. Carbon nanotubes have long been touted as promising building blocks for computers based on carbon rather than silicon. A main motivation towards this goal is the potential for circuits using carbon nanotube transistors to achieve high energy efficiency. Various carbon nanotube electronic circuit blocks have been demonstrated previously, but Max Shulaker et al. now reach a true milestone in the fields of carbon electronics and nanoelectronics by building a simple but functional computer made entirely from carbon nanotube transistors. Composed of 178 transistors, each containing between 10 and 200 carbon nanotubes, it runs a simple operating system and is capable of multitasking: it performs four tasks (summarized as instruction fetch, data fetch, arithmetic operation and write-back) and can run two different programs concurrently. The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy–delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies1,2. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems3,4.

A novel contact technique to reduce the effective Schottky barrier height on Ge and III–V high mobility semiconductors is described. Single metals are used in combination with an ultrathin dielectric to tune the metal/semiconductor barrier height toward zero by shifting or suppressing the strong Fermi-level pinning. Barrier height reduction in the metal-insulator-semiconductor (MIS) contact structure is verified through direct measurements and deduced from increased diode current and reduced contact resistance. Current demonstrations of the MIS contact have barriers as low as 0.05 eV for Er/SiN/n-Ge and 0.18 eV for Al/Al2O3/n-GaAs. The underlying physics is discussed along with the dependence of the minimum achievable contact resistance and barrier height on the metal, dielectric material, dielectric thickness, and substrate doping. For Ge, the MIS contact provides a possible solution to the low n-type Ge dopant solubility problem and allows for the fabrication of Schottky barrier field-effect transistors. For III–V semiconductors, the MIS contact allows for the use of a non-alloyed contact that is crucial for the scalability of III–V metal oxide semiconductor field-effect transistors.

Continuous monitoring of internal physiological parameters is essential for critical care patients, but currently can only be practically achieved via tethered solutions. Here we report a wireless, real-time pressure monitoring system with passive, flexible, millimetre-scale sensors, scaled down to unprecedented dimensions of 1 × 1 × 0.1 cubic millimeters. This level of dimensional scaling is enabled by novel sensor design and detection schemes, which overcome the operating frequency limits of traditional strategies and exhibit insensitivity to lossy tissue environments. We demonstrate the use of this system to capture human pulse waveforms wirelessly in real time as well as to monitor in vivo intracranial pressure continuously in proof-of-concept mice studies using sensors down to 2.5 × 2.5 × 0.1 cubic millimeters. We further introduce printable wireless sensor arrays and show their use in real-time spatial pressure mapping. Looking forward, this technology has broader applications in continuous wireless monitoring of multiple physiological parameters for biomedical research and patient care.

The conduction and switching mechanism of resistive random access memory (RRAM) is reviewed in this paper. The resistive switching in oxides is generally attributed to the conductive filament (made up of oxygen vacancies) formation and rupture in the oxide due to field assisted oxygen ion migration. As a model system for device physics study, HfOx based RRAM devices were fabricated and characterized. To identify the electron conduction mechanism, various electrical characterization techniques such as I-V measurements at various temperatures, low-frequency noise measurements, and AC conductance measurements were employed. It was suggested that the trap-assisted-tunneling is the dominant conduction mechanism. In order to explore the oxygen ion migration dynamics, pulse switching measurements were performed. An exponential voltage-time relationship was found between the switching time and the applied voltage. To obtain a first-order understanding of the variability of resistive switching, a Kinetic Monte Carlo (KMC) numerical simulator was developed. The generation/recombination/migration probabilities of oxygen vacancies and oxygen ions were calculated, and the conductive filament configuration was updated stochastically according to those probabilities. The KMC simulation can reproduce many experimental observations in the DC I-V sweep, pulse switching, endurance cycling, and retention baking, etc. The tail bits in the resistance distribution are attributed to the oxygen vacancy left over in the gap region due to a competition between the oxygen vacancy generation and recombination. To enable circuit and system development using RRAM, a compact device model was developed. The compact model, implemented in MATLAB, HSPICE, and Verilog-A, which can be employed in many commonly available circuit simulators using the SPICE engine.

Continuous monitoring of in vivo biological processes and their evolution at the cellular level would enable major advances in our understanding of biology and disease. As a stepping stone towards chronic cellular monitoring, we demonstrate massively parallel fabrication and delivery of 3D multilayer micro-Tags (μTags) into living cells. Both 10 μm × 10 μm × 1.5 μm and 18 μm × 7 μm × 1.5 μm devices containing inductive and capacitive structures were designed and fabricated as potential passive radio-frequency identification tags. We show cellular internalization and persistence of μTags over a 5-day period. Our results represent a promising advance in technologies for studying biology and disease at the cellular level.

Phase change nanodot arrays were fabricated using self-assembly diblock copolymer template PS-b-PMMA (polystyrene-poly (methyl-methacrylate)) and studied by time resolved X-ray diffraction. The size of the nanodots was less than 15nm in diameter with 40nm spacing. This method is quite flexible regarding the patterned materials, and can be used on different substrates. The crystallization behavior of small scale phase change nanodot arrays was studied for different materials, such as Ge15Sb85, Ge2Sb2Te5 and Ag and In doped Sb2Te. It was found that the nanodots had higher crystallization temperatures compared to their corresponding blanket films and crystallized over a broader temperature range.

The dose loss and transient enhanced diffusion of indium in silicon were studied as a function of dose. Indium was implanted into silicon through a 90 A oxide at 50 keV for doses ranging from 3x 1012 to 2x14 cm−2. These conditions provide peak concentrations that approximately range from 1x1018-1x1020 cm−3. After an RTA anneal at 1000°C for 5s, indium exhibits substantial motion at both the tail and peak regions for high doses. The enhanced diffusion is mostly over within 5s. There was not any observable enhanced diffusion in the tail region at the lowest dose although there was significant movement at the peak region. The dose loss correlates very well with the enhancement in the diffusivity. TEM images show that the amorphization dose lies between 3x1013 and 8x1013 cm−2. In spite of the amorphization, diffusion enhancement in the tail region still keeps increasing with dose, which is contrary to a model of “+1” interstitials and complete removal of interstitials in the regrown layer. The 550°C lh anneals show that the dose loss can partially be attributed to the sweeping of the dopant by the growing a/c interface. Previously, the solubility of indium has been estimated to be around 1–2×1018 cm−3. At high doses, significant movement is observed at the peak of the indium profile although the peak concentration exceeds the solubility level by at least an order of magnitude. This shows that indium is not precipitating into an immobile phase like antimony or boron.