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In this work the Si interstitial contribution of F+ implants in crystalline Si is quantified by the analysis of extended defects and B diffusion in samples implanted with 25 keV F+ and/or 40 keV Si+. We estimate that approximately 0.4-0.5 Si interstitials are generated per implanted F+ ion, which is in good agreement with the value resulting from the net separation of Frenkel pairs obtained from MARLOWE simulations. The damage created by F+ implants in crystalline Si may explain the presence of extended defects in F-enriched samples and the evolution of B profiles during annealing. For short anneals, B diffusion is reduced when F+ is co-implanted with Si+ compared to the sample only implanted with Si+, due to the formation of more stable defects that set a lower Si interstitial supersaturation. For longer anneals, when defects have dissolved and TED is complete, B diffusion is higher because the additional damage created by the F+ implant has contributed to enhance B diffusion.

Doping of thin body Si becomes very essential topic due to increasing interest of forming source/drain regions in fully depleted planar silicon-on-isolator (SOI) devices or vertical Fin field-effect-transistors (FinFETs). To diminish the role of the short-channel-control-effect (SCE) the Si layers thicknesses target the 10 nm range. In this paper many aspects of thin Si body doping are discussed: dopant retention, implantation-related amorphization, thin body recrystallization, sheet resistance (Rs) and carrier mobility in crystalline or amorphized material, impact of the annealing ambient on Rs for various SOI thicknesses. The complexity of 3D geometry for vertical Fin and the vicinity of the extended surface have an impact on doping strategies that are significantly different than for planar bulk devices.

The very large development of home and domestic electronic appliances as well as portable device has led the microelectronics industry to evolve in two complimentary directions : “More Moore” with the continuous race towards extremely small dimensions hence the development of SoCs (System on Chip) and more recently a new direction that we could name “More than Moore” with the integration of devices that were laying outside the chips and here the creation of SiPs (System in Package).These two approaches are not in competition one with the other: the paper will show some examples of integrated nano systems that use several SoCs.The technology we have developed is called Silicon Based System in Package. The first products using this technology are now in volume production and used mainly in the field of wireless communications.This new technology relies on four pillars. Passive integration is the first. Very efficient and high quality factor capacitors and inductors have been integrated, allowing the creation of complete modules including active devices, filters and decoupling capacitors. High-density MOS capacitors with 1-1000 nF capacitance, and as high values as 25-250+ nF/mm2 specific capacitance have been fabricated in macroporous Si-wafers, containing over 1 billion macropores. Typically an ESR less than 100 mÙ and an ESL less than 25 pH were found for capacitors over 10 nF. This novel concept is an important step forward in improving the stability of power-amplifier modules by replacing conventional SMD technology.Whereas generations with capacitors density of up to 100 nF/mm2 will be using “conventional” materials and structures, the next steps in the roadmap will call for new 3D structures and materials such as high-k dielectric.The second element is advanced packaging. New technologies, such as the assembly of Silicon chips onto other Silicon chips, also named “double flip chip” have been developed. This has been made possible thanks to the combination of the most advanced microbumping and die placement techniques. In addition to a tremendous reduction of size (up to a factor of 10 to 20) these techniques have also brought a better repeatability of system performance.The third element has been the development of design tools that allow a seamless system design for engineers used to IC design tools and flows. Our Design Environment allows co design of multiple technologies chips and their integration in a single system. This IC-like Design Environment has contributed a lot to the adoption of the technology.Testing is the fourth element and is one of the economical enablers of the technology. The key words are: “known good die”, RF test, system test, etc. Some innovative RF probing and full on wafer subsystem test will be shown. Even though efficient test is not vital for the technical feasibility of this system integration, it becomes very quickly one of the most important enablers, especially when we deal with very high volumes of production. The conclusion of the paper will be an open door to the future. Some innovations like the integration of light or even energy storage inside our SiPs will be presented.

A plasma-assisted atomic layer deposition (PA-ALD) process of titanium nitride (TiN) using TiCl4 precursor dosing and H2/N2 plasma exposure is presented. In situ spectroscopic ellipsometry revealed a growth rate at 400 °C of ∼0.7 A/cycle independent of precursor dosing. Varying the plasma exposure time changed the stoichiometry [N]/[Ti] of the films within the range ∼0.93-1.15. At 100 °C a relatively low chlorine impurity level (∼2 at. %) and low resistivity (∼200 νΔcm) were obtained for a ∼45 nm thick film. The growth rate was found to be considerably lower (∼0.3 Å/cycle) at this temperature. Using TEM imaging we found that PAALD TiN films can be deposited conformally in 20:1 aspect-ratio features (1.5 Êm width) but that the step coverage still needs to be improved, probably by a prolonged plasma exposure step.

In this work we investigate the diffusion of high-concentration ultrashallow boron, fluorine, phosphorus, and arsenic profiles in amorphous silicon. We demonstrate that boron diffuses at high concentrations in amorphous silicon during low-temperature thermal annealing. Isothermal and isochronal anneal sequences indicate that there is an initial transient enhancement of diffusion. We have observed this transient diffusion characteristic both in amorphous silicon preamorphized by germanium ion implantation and also in amorphous silicon preamorphized by silicon ion implantation. We also show that the boron diffusivity in the amorphous region is similar with and without fluorine, and that the lack of diffusion for low-concentration boron profiles indicates that boron diffusion in amorphous silicon is driven by high concentrations. Ultrashallow high-concentration fluorine profiles diffuse quite rapidly in amorphous silicon, and like boron, undergo a definite transient enhancement. In contrast, ultrashallow high- concentration phosphorus and arsenic profiles did not significantly diffuse in our experiments.

High-density MOS capacitors have been fabricated with ∼ 30 nF/mm2 specific capacitance on highly-doped Si-wafers with arrays of macropores with ∼ 2 μm diameter. Using the Bosch process [1] these pores were dry-etched to depths of ∼ 30 μm or more. The enlarged Si-surface thus obtained serves as a substrate for capacitors fabricated by fully MOS-compatible processing.Wafers were fabricated with a top electrode of poly-Si and Al and ‘ONO’ (i.e. oxide / nitride / oxide) dielectric stacks showing 7–10 MV/cm electrical breakdown field and leakage < 1 nA/mm2 @ 20 V. These wafers were thinned to 380 μm and sawn into dies, representing 40 nF capacitors. Typically low loss factors such as ESR < 50 mΩ and ESL < 20 pH and resonance frequencies of ∼ 0.1 GHz were found for 40 nF capacitor dies. Next, 40 nF dies were mounted by wire bonding on Al2O3 or laminate substrate as supply-line decoupling capacitors in complete GSM power amplifier test modules. RF decoupling and transmission were measured and compared to identical test modules with conventional discrete ceramic capacitors. The MOS capacitors showed very efficient decoupling, resulting in superior signal stability as measured in the 0 – 1 GHz range (less noisy, free from oscillations).The new capacitor is very suitable for integrated decoupling purposes, e.g. supply-line decoupling in RF wireless communication and analog and mixed-signal systems.

CVD-grown lightly C-doped superlattices with peak C concentrations of 2.1018/cm2 and 2.1019/cm2 were annealed in NH3, N2/H2, N2, and O2 ambient gases to investigate the influence of a range of point-defect conditions on C diffusion at the nanometer scale. C profiles were measured by secondary-ion mass spectroscopy. The profiles exhibit exponential-like diffusion consistent with a ‘long hop’ diffusion process with a characteristic migration length λ (=19 ± 3 nm at 850°C). Within experimental errors the value of ë is the same for all the ambient gases used, whereas the migration frequency g increases by two orders of magnitude as the ambient gas is changed from NH3 ambient (interstitial undersaturation) to O2 ambient (interstitial supersaturation), and decreases as a function of C concentration in the as-grown superlattice. The results confirm that C diffuses predominantly by a kick out mechanism under nearequilibrium diffusion conditions. Initial results support the chemical-pump model for suppression of diffusion in C-doped silicon.

The work function of a metal gate electrode has been adjusted with the introduction of nitrogen by solid-source diffusion from an over-stoichiometric TiN1+x layer. RBS measurements have shown that measurable concentrations of nitrogen can be diffused into a 10nm Ta layer at moderate anneal temperatures (>500°C), and that this concentration increases with temperature in the range 500-1000°C. Capacitance-voltage measurements have been carried out on 10nm tantalum layers on Al2O3. These measurements have indicated that the work function of tantalum changes by -0.08eV due to the presence of the over-stoichiometric TiN1+x covering layer during anneal (800°C/30”). Similar C-V measurements have been carried out on 10nm molybdenum layers on SiO2 and on Al2O3 dielectrics. These have shown that the work function of molybdenum is substantially different for metal stacks with the TiN1+x covering layer after a similar anneal. The work function changes by -0.52eV for molybdenum on SiO2 and by -1.1eV for molybdenum on Al2O3. The results suggest great potential for molybdenum as a candidate for a single-metal dual-work function approach to integrating metal gates into future CMOS technologies.

This paper addresses the optimization of ion implantation and rapid thermal annealing for the fabrication of shallow junctions and the activation of polycrystalline silicon gates in deepsubmicron CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by combining low-energy B and As implantation with spike annealing. In addition, experiments using B doping marker superlattices were performed to identify the critical physical effects underlying dopant activation and diffusion. The combination of high ramp rates (∼100 °C/s) and ∼1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without inducing significant thermal diffusion after TED has completed. MOS capacitors were used to identify the implantation and annealing conditions needed for adequate activation of the gate electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing times while improving the gate activation level. The fine-grained crystal structure enhances the de-activation of B dopants in PMOS gates during the thermal treatments following gate activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent 0.18 μm device performance. The feasibility of spike annealing and poly-Si gate materials for 100-nm technology was proven by full integration using gate lengths down to 80 nm.

The ripening of ion-beam generated point defects into extended defects has been investigated in detail. The interstitial supersaturation has been extracted from boron marker-layer diffusion after annealing under non-equilibrium defect conditions. We measured a very high initial supersaturation followed by a decrease over many orders of magnitude with a characteristic “plateau” related to the presence of {113} defects. A continuum inverse model has been used to properly describe the ripening of point defects into clusters and their evolution in the presence of a remote sink, e.g. the surface. It evidences that a nonconservative Ostwald ripening process takes place inside the defect band during the annealing and sustains the interstitial supersaturation. The model reveals moreover an oscillatory behaviour of dissociation energies of the nanometer-sized defects which are responsible for the initial high supersaturation. These defects are believed to be {113} precursors.

The sol-gel system iron triethoxide - tetraethylorthosilicate (TEOS) with the Fe/Si atomic ratio ranging from 0 to 1 has been investigated. Our study leads to the conclusion that the annealing method of the hydrolyzed precursor film determines the type of solid film formed. Annealing by Rapid Thermal Processing (RTP) with its high heating and cooling rates yields amorphous, glassy iron silicate films. These films result from polycondensation reactions between Si-OH and Fe-OH groups of the hydrolyzed precursors forming Fe-O-Si and Si-O-Si bonds. These bonds show a characteristic vibration band in FTIR spectra, which is most intense for Fe/Si = 1, and shifts for increasing Fe/Si ratio from 1073 down to 965 cm-1.The iron silicate film with Fe/Si =1 obtained by RTP displays an optical absorption band around 320 nm, which indicates that Fe3+-ions have a tetrahedral coordination similar to the Si4+-ions in Si02 and glass with tetrahedrally coordinated silicon and iron ions linked by bridging oxygen atoms. The films, typically 0.1 μm thick, annealed by RTP have a smooth, mechanically hard surface. This glassy structure can be formally presented as FeSiOx. Conventional furnace heating with low heating/cooling rates yields nanocrystalline films with predominantly Si-O-Si bonding in grains with sizes below 40 nm. More structural and chemical investigation is needed to elucidate the details of the structure and the formation mechanism of the amorphous compound, but we can conclude that the cooling rate has a direct effect on the degree of non-crystallinity of the compound. The high cooling rate of RTP will retain the Fe-O-Si bonds formed in a state of inequilibrium, and “quench” them in an amorphous, metastable glass compound, whereas slow cooling gives rise to nanocomposite film formation.

A new emerging application area for Rapid Thermal Annealing (RTA) may be in the manufacturing of thin-film recording heads for high-density (hard disk drive, video, audio and data tape) recording. To that end we co-designed a new commercial reactor with an external electromagnet to anneal thin soft-magnetic films (nanocrystalline iron alloys) deposited on ceramic wafers of up to 150 mm diameter. The electromagnet generates a field controllable up to 660 Oe (52.8 kA/m). It is completely homogeneous in direction (i.e. fully parallel field lines) across the entire wafer area. Wafers can be annealed either statically, or while rotating (up to 120 rpm), or in two subsequent heating steps with a 90° wafer rotation in between.Nanocrystalline Fe-Nb-Si-N layers have better soft-magnetic properties after Rapid Thermal Magnetic Annealing (RTMA) in a static magnetic field than after conventional furnace annealing in a static field. Temperature-programmed resistance measurements and Transmission Electron Microscopy (TEM) show that the first nanocrystalline, body-centered cubic iron grains start growing already as of 350 °C from the amorphous as-deposited film, whereas the desired segregation of NbN starts only as of 530°C. RTA can be used to promote the kinetics of the segregation of NbN along the boundaries of nanocrystalline iron nuclei. This prevents the iron grains from further growth: with RTMA the iron alloys show smaller nanocrystalline iron particles (order: 10 nm) as observed by TEM.

The Giant Magnetoresistance effect with high field-sensitivity was recently discovered in multilayers of alternating ferromagnetic and non-ferromagnetic layers. Some of these layer structures may find industrial application in miniaturized sensor and high-density digital magnetic recording technologies which require materials with large changes in electrical resistance at low magnetic fields.In this paper we report on Rapid Thermal Annealing experiments done on a series of multilayers of alternating thin permalloy (Ni80Fe20) and silver films. The layers were sputter deposited on thermally oxidized Si (100) substrates. Samples were annealed in nitrogen at temperatures ranging from 280 to 340 °C for 30 seconds to 10 minutes, yielding magnetoresistance data as high as 5% and a maximum field sensitivity of 4.6% per kA.m-1. X-Ray diffraction analysis, showing the gradual formation of an Ag (111) shoulder peak at 20 = 38.3° upon annealing, supports a recently published hypothesis that the appearance of the GMR effect is annealinduced by a change of the microstructure due to diffusion, causing notching and disruption of the permalloy layers in the superlattice.

This paper reviews the current status, problems and options in RTP system and process design. Some commercial systems will be discussed along with some improvements that can still be made in temperature reproducibility, process control and yield. This includes some recent developments in temperature reproducibility by compensated emissivity control.Uniformity issues regarding temperature and process gas hydrodynamics are highlighted in relation to reactor design. Especially in CVD applications, where radiative heat transfer may not longer dominate convective and conductive heat transfer, modeling and visualization of gas flow patterns are becoming increasingly important. Here, reactor design should be such that a laminar flow regime is reached without turbulence and without chemical memory effects upon switching to other gas compositions. Some flow visualization results are illustrated.Some new options for micro- and nanocrystallization reactions are presented before we conclude with a technology roadmap to the 1-Gbit era.

The main factors influencing the thermal performance (and thus product yield) of a rapid thermal processor are the heat source, the reaction chamber, the temperature measurement system, and as complicating factors, their total configuration and the optical wafer properties.The characteristics of 19 currently available commercial RTP systems are highlighted with focus on temperature control including the spectral characteristics and measures to suppress perturbations due to stray radiation.In addition recent developments and trends in the system configuration and in the optimization of temperature or layer thickness control are discussed. The improvements in temperature control focus especially on in situ temperature control, irrespective of wafer condition, and at system constructions that optimize dynamic temperature uniformity. Some novel optical process control and novel system design aspects to compensate for emissivity changes and temperature non-uniformity are included.