Search

We present design equations for error function (or “S-graded”) graded buffers for use in accommodating lattice mismatch of heteroepitaxial semiconductor devices. In an S-graded metamorphic buffer layer the composition and lattice mismatch profiles follow a normal cumulative distribution function. Minimum-energy calculations suggest that the S-graded profile may be beneficial for control of defect densities in lattice-mismatched devices because they have several characteristics which enhance the mobility and glide velocities of dislocations, thereby promoting long misfit segments with relatively few threading arms. First, there is a misfit-dislocation-free zone (MDFZ) adjacent to the interface, which avoids dislocation pinning defects associated with substrate defects. Second, there is another MDFZ near the surface, which reduces pinning interactions near the device layer which will be grown on top. Third, there is a large built-in strain in the top MDFZ, which enhances the glide of dislocations to sweep out threading arms. In this paper we present approximate design equations for the widths of the MDFZs, the built-in strain, and the peak misfit dislocation density for a general S-graded semiconductor with diamond or zincblende crystal structure and (001) orientation, and show that these design equations are in fair agreement with detailed numerical energy-minimization calculations for ZnSySe1−y/GaAs (001) heterostructures.

The design of lattice-mismatched semiconductor devices requires a predictive model for strains and threading dislocation densities. Previous work enabled modeling of uniform layers but not the threading dislocations in device structures with arbitrary compositional grading. In this work we present a kinetic model for lattice relaxation which includes misfit–threading dislocation interactions, which have not been considered in previous annihilation–coalescence models. Inclusion of these dislocation interactions makes the kinetic model applicable to compositionally graded structures, and we have applied it to ZnSe/GaAs (001) and ZnSySe1−y/GaAs (001) heterostructures. The results of the kinetic model are consistent with the observed threading dislocation behavior in ZnSe/GaAs (001) uniform layers, and for graded ZnSySe1−y/GaAs (001) heterostructures the kinetic model predicts that the threading dislocation density may be reduced by the inclusion of grading buffer layers employing compositional overshoot. This “dislocation compensation” effect is consistent with our high-resolution x-ray diffraction experimental results for graded ZnSySe1−y/GaAs (001) structures grown by photoassisted metalorganic vapor-phase epitaxy.

We have conducted a theoretical study of the equilibrium strain and misfit dislocation density profiles for “S-graded” buffer layers of InxGa1−xAs on GaAs (001) substrates in which the compositional profile follows a normal cumulative distribution function. On the basis of this modeling work we show that the S-graded layer exhibits misfit dislocation-free regions near the substrate interface and the free surface (or device interface). The equilibrium peak misfit dislocation density as well as the thicknesses of the dislocation-free regions may be tailored by design of the compositional profile; this in turn should enable minimization of the density of electronically active threading dislocations at the top surface. S-graded buffer layers may therefore facilitate the achievement of metamorphic device structures with improved performance compared with similar structures having uniform or linearly graded buffers.