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Software-defined networking (SDN) has become the technology of choice for designing the next-generation network infrastructure that is featured with high-volume traffics, rapidly increased scale, and dynamic nature. Furthermore, to deploy multiple controllers in the control plane of SDN is widely considered with the aim of improving the stability and reliability of the network. This paper presents an integrated framework for a comprehensive multi-controller management in SDN. The proposed framework is comprised of a network planning phase and a runtime maintenance phase. Novel algorithms are proposed in the network planning phase to estimate the required number of controllers in the network, to determine the nodes for placing the controllers, and to assign the switch to its managing controller. Moreover, these algorithms are designed by mitigating the problems of device isolation and controller overload such that the reliability and stability of the control plane can be enhanced. In addition, a mechanism based on the State Behavior Tree is proposed in the runtime maintenance phase of the framework. This mechanism dynamically manages the loading of the controller during the execution time so that the occurrence of the controller overload is minimized. The experimental results show that, compared to the prior arts, the proposed framework reduces the isolation probability by up to 89% and increases the device connectivity by up to 34%. The occurrence of the controller overload during runtime is also significantly decreased.

This paper presents the VLSI architecture of a highly-efficient and low-complexity Generalized Frequency Division Multiplexing (GFDM) receiver based on the joint Minimum Mean Square Error (joint-MMSE) approach. To be specific, a novel data processing flow is proposed in this paper where the bit reverse permutation after the FFT operation and the shuffle permutation are conducted concurrently. As a result, the processing delay is greatly reduced and the memory requirement for the temporary storage is saved. Based on the designed data flow, the VLSI architecture of the joint-MMSE GFDM receiver is presented. A novel folded structure is proposed so that the arithmetic and storage elements are utilized in a time-sharing manner and the area complexity is decreased. These elements are also architected with high configurability to support various processing modes. Moreover, a novel memory-access algorithm and address-generation circuit is designed to efficiently access the memory module and to mitigate the data conflict when supporting different processing modes. The proposed design is synthesized using TSMC 90 nm technology at operating frequency of 200 MHz. The post-synthesis estimation shows that this architecture occupies an area complexity of 492.6 kGEs. The analyses results illustrate that the proposed data flow leads to a 16% reduction in delay and complexity compared to the conventional approaches. Furthermore, the proposed design enhances the Efficiency by 4.7x compared to the state of the art work.

Fast Fourier Transform (FFT) processor is a paramount signal processing component in MIMO-OFDM wireless communication systems. Furthermore, novel applications introduced in 5G incur much more rigorous requirements for FFT designs including complexity, latency, and re-configurability. This paper presents the VLSI architecture design and circuit implementation of a FFT processor that is jointly optimized for low-latency, low-complexity, and configurability. Specifically, the proposed architecture processes two data streams concurrently and supports power-of-two FFT sizes from 64 to 2048 symbols. Moreover, a novel data-processing sequence is presented so that data streams are processed in a time-multiplexing manner and an efficient hardware-sharing architecture can be designed. In addition, a highly efficient I/O reorder mechanism is proposed so that the memory elements are shared between processing stages and the efficiency for utilizing memory components is enhanced. Based on the architectural optimizations, two FFT processors are realized. The ultra-low latency design achieves a latency of 4 μs with 41% area reduction compared to the comparable designs. On the other hand, the ultra-low complexity structure achieves a latency of 25 μs with 24% area reduction compared to the state-of-the-art implementations.

We investigate whether the gains are greater for banks that conduct mergers and acquisitions (M&As) during banking crises than during non-crisis periods. We contribute to the literature by examining 1984 M&As using global banking sample from 106 countries (areas) during 1994 ~ 2009. We find the synergistic gains of acquiring banks during banking crises are larger than those during non-crisis periods. We further find that such gains are greater when acquiring weak targets, for acquirers in developed countries, and for acquirers in domestic M&As. This study confirms that a banking crisis is an appropriate time for banks to conduct M&As.

This paper presents a novel algorithm and VLSI architecture of motion estimation (ME) for high efficiency video coding systems. The proposed algorithm examines a much smaller set of search candidates and thus greatly reduces the computational complexity. Furthermore, in order to strike a balance between the quality of the Video and the efficiency of the system, this algorithm possesses the advantages that the number of search candidates is adaptive to the characteristic of the Video content. The simulation results show that, compared to the HM reference software, the proposed algorithm leads to a 96% reduction in search candidates with only 1.98% increment in average bitrate. Based on this algorithm, a hardware-efficient VLSI architecture of ME is designed and implemented with 90 nm technology. The experimental results show that, occupying the area complexity of 274.5 kGE, the presented design achieves 60 frames per second with resolution of 3840 × 2160 at the frequency of 201 MHz. The proposed ME system enhances the hardware efficiency by at least 50% compared to the prior works.

In order to guarantee the Quality of Service (QoS) requirements of multimedia network, based on the concept of Software Defined Networking (SDN) and OpenFlow protocol, this paper presents the hardware and software co-design of a configurable QoS scheme for video streaming. Specifically, we present the architecture of an OpenFlow switch where the allocated network bandwidth for each multimedia traffic can be dynamically configured by the SDN controller. The detailed structures of software and hardware components are illustrated in this paper. For proof of concept, we realize the proposed switch based on a System on Chip (SoC) platform. We first implement a basic OpenFlow switch based on the state-of-the-art NetFPGA-CML platform. This design occupies 40% of total resources, and is promising for further researches and developments of multimedia networks. We realize the proposed OpenFlow switch with configurable QoS on this platform and carry practical experiments and measurements. The experimental results show that the proposed configurable QoS scheme enhances the QoS and received PSNR of the video streaming.

This paper presents the VLSI architecture and implementation of the highly efficient fractional motion estimation (FME) for High Efficiency Video Coding (HEVC) systems. In this design, the processing sequence of input pixels is highly optimized so that large parts of the hardware resources in the interpolator circuit are shared and the area complexity is greatly reduced. In order to further enhance the efficiency of hardware utilization and to achieve high throughput, the sum of absolute transformed differences circuit is realized using a pipelined time-multiplexing scheme, and the hardware-sharing structure is utilized to reduce the required computation components. Furthermore, comparing to the literature based on HEVC systems, this design enhances the rate-distortion performance by supporting more prediction modes. The proposed design has been synthesized, placed, and routed through cell-based design flow using TSMC 90-nm technology. The post-layout estimations show that, occupying the area complexity of 525.4 kGE, the presented FME architecture achieves 39 frames per second (fps) with resolution of 3840 × 2160 and 29 fps with resolution of 7680 × 4320. In addition, comparing to the prior art that supports 30 fps and the same number of prediction modes, this design achieves a 2 × improvement of hardware efficiency.

We have synthesized two isostructural mononuclear cobalt(III) complexes [1]NO3⋅3H2O and [1]NO3⋅CH3CO2H⋅H2O {[1] + = [Co(1,10-phenanthroline)2Cl2]+} and characterized by single crystal X-ray structural analyses. Mass spectral studies of the complexes indicate both the compounds to produce identical cationic species viz., [Co(phen)2Cl2]+ in methanol solution. [1]+ has been evaluated as model system for the catechol oxidase enzyme by using 3,5-di-tert-butylcatechol (3,5-DTBC) as the substrate in methanol medium, which revealed that the cationic complex efficiently inhibits catalytic activity with kcat value 9.65 ×102 h−1. [1]+ cleaved pBR 322 DNA without addition of an activating agent. Further, the anti-cancer activity of [1]+ on human hepatocarcinoma cell line (HepG2) has been examined. The induction of apoptosis induced in the cell line was assessed base on the changes in cell morphology, which showed the efficacy of [1] + to induce apoptosis in 53% of cells during 24 h treatment. Interestingly, the observed IC50 values reveal that [1]+ brings about conformational change on DNA strongly and exhibits remarkable cytotoxicity.

This study investigates whether firms politically connected to the ruling party can mitigate financial constraints and increase their investments. Data on Taiwan-listed companies from 1991 to 2010 are used to answer the preceding issue. Results indicate that firms connected to the ruling party that transitioned into power can mitigate financial constraints, but results do not hold for firms connected to the opposition party that transitioned out of power. Firms connected to both parties have similar results with those connected to the ruling party, but the diminishing effect is weaker than those connected to the ruling party. Results further indicate that financially constrained firms can increase their investment when they have political connections to the ruling party. Finally, firms with strong connections can reduce financial constraints more effectively.

We investigate the effect of sovereign credit ratings on bank credit ratings, known as the sovereign effect. Our study differs from the literature in three respects. First, we examine whether bank ratings below, at, or above the sovereign ceiling impact the sovereign effect. We find that the sovereign effect holds in all cases. Next, we consider the asymmetric impact of the sovereign effect on bank ratings with or without the ceiling effect. We find that a downgrade exhibits a stronger sovereign effect than an upgrade. Third, we examine whether the asset deterioration or the stable foreign fund hypotheses are possible explanations for the sovereign effect. Our results support both hypotheses.

In this study, we reinvestigate the question of whether government banks are inferior to private banks. We use cross country data from 1993 to 2007 to trace the different types of government banks. These types comprise banks that acquire distressed banks, normal banks, or no banks at all. Contrary to common belief, the evidence shows that unless government banks are required to purchase a distressed bank because of political factors (the government’s role), their performances are at par with that of private banks. This fact particularly holds true in countries with poor records on political rights and governance.

This paper investigates whether political connections improve the access of firms to financing. We propose three hypotheses to prove that political benefits exist. First, do politically connected firms obtain preferential treatment for bank loans? Second, if these firms do obtain preferential treatment, do they benefit from government-owned banks (GOBs) more than from privately owned banks? Third, is the preferential treatment from GOBs enhanced during presidential election years? We examine these three questions by using detailed data on political connections and 69,332 individual bank-loan contracts for listed firms in Taiwan from 1991 to 2008. The empirical results generally support our hypotheses.

In recent work, a graphical modeling construct called "topological patterns" has been shown to enable concise representation and direct analysis of repetitive dataflow graph sub-structures in the context of design methods and tools for digital signal processing systems (Sane et al. 2010). In this paper, we present a formal design method for specifying topological patterns and deriving parameterized schedules from such patterns based on a novel schedule model called the scalable schedule tree. The approach represents an important class of parameterized schedule structures in a form that is intuitive for representation and efficient for code generation. Through application case studies involving image processing and wireless communications, we demonstrate our methods for topological pattern representation, scalable schedule tree derivation, and associated dataflow graph code generation.

In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

The transition economies are known to have quite different market structures from the market economies. State-owned banks accounts for a major part of the financial sector in East European countries before the transition period. Since the input prices of the sector are frequently under the control of those governments, the misallocated resources may incur the loss of economic efficiency. This paper attempts to gauge the technical and allocative efficiency using unbalanced panel data of 340 banks from 14 transition countries under the framework of the Fourier flexible shadow cost function. Accommodating technical and allocative efficiencies simultaneously, as suggested by Atkinson and Cornwell (Int Econ Rev 35:231–243, 1994a) and Kumbhakar and Wang (J Econom 134:317–340, 2006a), avoids potential specification errors and leads to consistent parameter estimates. The average total cost savings resulting from greater technical and allocative efficiency are around 28.31 and 7.13%, respectively. Foreign-owned banks are found to be the most economically efficient. The enforcement of financial liberalization does gradually improve upon the sample banks’ technical efficiency. The allocative inefficiency arises from over capitalization and excess funds. Scale diseconomies appear to prevail in the sample states with a few exceptions.

This study presents the nonlinear relationship that exists between financial development and economic growth. This study applies the flexible nonlinear regression model of Hamilton (Econometrica 69(3):537–573, 2001) because it imposes no specification restrictions. Two empirical results are obtained. First, an inverted U-shaped relation between banking sector development and economic growth is identified. Namely, the two variables are positively linked before the turning point, but negatively linked after it. Second, a positive relationship with asymmetric √-shape between stock market development and economic growth is found.

In this article, we examine the effect of corporate social responsibility (CSR) on firms’ financial performance (CSR-effect). Two competing hypotheses, social impact hypothesis and shift of focus hypothesis, are proposed to investigate this issue, where the former suggests that CSR has a positive relation with performance and the latter are opposite. In order to ensure the CSR-effect is not contaminated by other factors or samples are randomly drawn, we employ four matching methods, Nearest, Caliper, Mahala and Mahala Caliper to match the samples of CSR (CSR-firms) and without CSR (NonCSR-firms) with similar characteristics. Although four methods yield slightly different results, firms engaging in CSR activities tend to obtain significantly higher values on pretax income to net sales and profit margin, and adopting CSR at the very least not deteriorate the performance of firms, making our conclusion favors the social impact hypothesis and against shift of focus hypothesis in Taiwan. Thus, ambition and conscience are not conflicting with each other.

To many, recent allegations of accounting fraud (or earnings management; EM) at Enron, coupled with similar ones at many other corporations, are a strong indication of a serious decay in business ethics. In academics, this raises the concern between EM and corporate social responsibility (CSR). Since it has neither been documented, nor globally tested whether CSR mitigates or increases the extent of EM, three kinds of EM are studied: earnings smoothing, earnings aggressiveness, and earnings losses and decreases avoidance. The extents to which financial characteristics and institutional variables have an impact on the extent to which companies conduct EM are also tested. Our study investigates whether the CSR-related features of 1,653 corporations in 46 countries had a positive or negative effect on the quality of their publicly released financial information during the 1993–2002 period. There is no question that with a greater commitment to CSR, the extent of earnings smoothing is mitigated, that of earnings losses and decreases avoidance is reduced, but the extent of earnings aggressiveness is increased.