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Carrier selective contact (CSC) architecture is one of several promising candidates for high-efficiency silicon solar cells operating close to the thermodynamic limit. However, an industrially feasible process is lacking for manufacturable CSC cells. Specifically, although evaporated molybdenum oxide (MoOx) has been actively researched as a hole selective layer, a more industry-compatible deposition process is critically needed. Atomic layer deposition (ALD) has been widely employed in the industry for material stacks requiring precise thickness control and uniformity. In this paper, we present a performance analysis of CSC solar cells fabricated using ALD MoOx as the hole selective layer. As a first step, the standard ALD recipe was modified to obtain sub-stoichiometric MoOx with a higher work function due to increased oxygen vacancy concentration. The modified MoOx recipe resulted in low open-circuit voltage values in fabricated not-passivated CSC solar cells. A 4 nm thick amorphous silicon layer inserted in the hole selective stack showed significant improvement in minority lifetime but worse solar cell performance due to increased series resistance. Besides indicating a strong trade-off between passivation and series resistance, the solar cell data highlights series resistance as a key performance limiter in CSC solar cells.

We propose a parasitic BJT-based zero capacitor random access memory (Z-RAM) cell suitable for stand-alone memory applications. In this Z-RAM cell, high-bandgap TiO $$_2$$ is used as the source/drain material and silicon as the channel of an n-channel fully depleted silicon-on-insulator MOSFET. Using well-calibrated TCAD simulations, we demonstrate the programming of the proposed Z-RAM cell at low drain voltages, which is a major advantage from an application perspective. At low drain voltage, hole storage is initiated by band-to-band tunnelling, which is subsequently taken over by impact ionization. Large valence band offset between TiO $$_2$$ and Si ( $$\varDelta { E }_\mathrm{V }\approx$$ 2 eV) is utilized for storing larger number of excess holes inside the body for a longer time. This leads to the improvement of both sense margin and retention time compared to an all-silicon Z-RAM cell. We predict a retention time of 2 s and 70 ms at $$T=300$$ K and 358 K, respectively, for device gate length of 30 nm. We have optimized the device design to obtain a write ‘0’ time of 6 $$\upmu$$ s. Multiple non-destructive reading operation for the proposed Z-RAM cell is also demonstrated.

A high efficiency (> $$18\%$$ ) industrial large area crystalline silicon wafer solar cell fabrication process generally requires industrial equipment with large footprint, high capital and running costs. Stricter processing window, continuous monitoring and automated functioning are the reasons for it. However, for any conventional laboratory (lab) it is always difficult to manage these requirements with limited available lab space or insufficient fund and other related resources. In this work, we report a novel way to fabricate high efficiency full area aluminium back surface field monocrystalline silicon wafer solar cells in our lab using low-cost processing with small-footprint fabrication tools for 6 inch pseudo-square industrial wafers. The novelty of our work includes optimization of every fabrication process step, e.g., texturization, emitter diffusion, emitter passivation and anti-reflection coating deposition, edge-isolation, screen printing and co-firing individually. These modifications include tuning of processing tools and processes, utility changes and inclusion of additional process steps. Beaker-based chemical processes, manual diffusion furnace, introduction of low temperature oxidation, low temperature silicon nitride deposition processes, plasma-edge isolation tool, single manual screen printer, single oven drying of metal pastes and co-firing using rapid thermal processing tools were used at our lab. For our cells, actual and active area efficiencies of 18.5 and 19% (measured under AM1.5G 1 Sun condition), respectively, were achieved.

We here present, metal nanocrystal (NC) formation statistics (size, density, occupancy or area coverage) on different high dielectric constant (high-K) materials which may be used as tunnel dielectric or intermetal dielectric in flash memory devices. Four important high-K materials viz. SiO2, Al2O3, HfO2 and Si3N4 are chosen for this purpose and the nanocrystal formation statistics has been found to be strongly dependent on dielectric. Among all the four dielectrics, smallest size nanocrystals with largest density are obtained on Al2O3 dielectric while on HfO2 bigger size nanocrystals are formed. This difference in nanocrystal size and density on different dielectrics is attributed to the different surface properties of these materials.

This paper presents an overview of Ni-alloy (Ni, Ni-Pt and Ni-Ta) silicide development for the 45 nm node and beyond, including applications to self-aligned silicide (SALICIDE) processes, reaction with SiGe and strained Si on SiGe, and applications to fully silicided (FUSI) gates. Key SALICIDE issues addressed include the use of spike or low temperature rapid thermal processes (RTP) to control silicidation and junction leakage on small features, factors affecting the formation of epitaxial pyramidal NiSi2 grains, and NiSi thermal stability and agglomeration kinetics. Alloying with Pt or Ta is shown to improve thermal stability of NiSi films, although with quite different behaviors. While Pt is incorporated predominantly in solution in NiSi, Ta segregates to the surface of the films. Ni-Pt alloy silicides were also found to achieve low sheet resistance on narrow gates, low contact resistivity and low junction leakage, making them attractive for CMOS applications. For the Ni/SiGe reaction, a narrower RTP process window for low sheet resistance and a lower activation energy for agglomeration were observed when compared to the Ni/Si reaction. The lower thermal stability was correlated to Ge segregation from the Ni(SiGe) films. The Ni/doped poly-Si reaction was studied for FUSI gate applications, showing a retardation of the silicidation kinetics for high B doses and a large pile- up of dopants (for As, B or P) at the NiSi/SiO2 interface due to dopant snowplow during silicidation. The work function (WF) of NiSi was observed to shift with the addition of dopants, effect attributed to modifications of the interface dipole by the pile-up of dopants. No significant degradation was observed when comparing gate oxide breakdown statistics for Ni FUSI to conventional poly-Si gates. The process window for a FUSI gate-last process (performed after S/D Ni silicidation) was evaluated showing a potential integration problem due to possible degradation of the S/D silicide during the FUSI gate reaction.