Search

This chapter presents an FPGA-based ECG system with telemonitoring facility. There are several methods of recording and transmitting ECG signals. A classical recording in health centers, then ambulatory ECG recordings and tele­metry monitoring the patient in and round medical center. The system presented in this chapter has a provision to transmit the ECG data through the serial modem for diagnosis by the expert cardiologist. In order to facilitate this, a communication protocol is designed and implemented in VHDL. The objective of this work was to study a modem based transmission of the ECG using telephone lines. Using this system the ECG of the patients was successfully transmitted to the expert medical professionals for immediate diagnosis. The design is implemented on a Xilinx Spartan 3E FPGA. The extent of the resources used indicates plenty of room for incorporating additional functionality which has been integrated and described elsewhere by the authors [96]. The system implemented here used with the control monitor center having trained medical staff could enable round the clock monitoring of few thousands of patients. With pre-paid service the patients might get the economical benefits and efficient way of monitoring than with classical recording of the ECG signal.

Embedding a soft IP core inside an FPGA has many advantages such as customization, design reuse, accelerating the design cycle and narrowing the time to market window thereby enhancing the productivity. In view of all the above mentioned advantages, the FPGA based systems are now penetrating the embedded arena which has marked the take off of the configware rather than the traditional embedded hardware and software. The complexity of the FPGA based SoCs in an Embedded paradigm has now been addressed by the designers by using the configware libraries that comprises of the soft IP cores. The design techniques pertaining to the soft IP cores are now regarded as the evolutionary techniques and the novel design methodologies of the Embedded Systems has comes out to be just an analytical marriage of the above mentioned soft IP cores. Pre-designed and pre-verified soft IP cores such as the ones designed in this chapter addresses the pertinent issues such as time to market, performance, area, power metrics etc. Further designing such soft IP cores in Handel C facilitates maximum flexibility and reconfigurability to match the requirements of a specific embedded design application. All the cores reported in this chapter have been verified/prototypes on the Xilinx Starter kit.

With the growing popularity of Internet and extensive use of E-mail as a communication media, the volume of Spam mails has seen to be growing at a phenomenal rate. The growing volume of Spam mails as well as their mutating nature annoys people and affects work efficiency significantly. The unsolicited emails or Spam’s used to be deliberated of as just a nuisance, in the past few decades, however in the last few years; their annoyance has reached to epidemic proportions. Thus the Spam mails have has really become a nightmare for every email user. This chapter presents Anti-Spam solution prototyped on Xilinx Spartan 3e FPGA and designed using Handel C. We have adopted the hardware-software co-design methodology and the same is described from scratch. Two IP cores have been designed viz. Content Addressable Memory (CAM) and Bloom Filter in Handel C and the same have been deployed on the Spartan 3e FPGA along with the customizable version of Microblaze. The main contribution is reporting the technical know how related to the co-design aspects that comprehends synergic mixture of soft IP cores of the content addressable memory (CAM) and bloom filter realized both in hardware and software with the Xilinx Microblaze processor. The toolset used for the hardware-software co-design is the Xilinx Embedded Design Kit (EDK). The design flow comprises of the IP core design in Handel-C, embedded in EDK driven by the central customized core of Microblaze.

In an increasingly digital domain of applications, the Digital Signal Processing (DSP) has become inevitable. With the outside environment predominantly analog, its conversion into the digital domain in order to facilitate the benefits of the matured DSP technology is also mandatory. Many a times the analog to digital converter performance becomes the bottleneck in advanced instrumentation and DSP applications. This chapter presents a Vernier Time to Digital Converter (TDC) with resolution less than 30 pS, implemented on SPARTAN III FPGA. Detailed description of the TDC using schematic editor and Verilog code ring oscillator, phase detector and counter have been described in this chapter.