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Tremendous and inescapable application of full adder adds impetus to its optimization till high-end performance. Use of full adder propels the design engineer to unearth various digital circuits, whose implementation otherwise would not be a cakewalk. This paper exhumes finest 3-bit parity checker in terms of power dissipation (PWR) and energy-delay product (EDP) variability. MCML (MOS Current Mode Logic) based implementation is practiced to improvise the circuit. Further, in this treatise, above mentioned 'CNFET-based 3-bit MCML parity checker' (used as full adder) and Transmission Gate based multiplexer is used to implement a novel design of '4-Bit 4-Tube CNFET based ALU' at 16-nm Technology Node. This CNFET-based ALU thus implemented is further compared with its CMOS counterpart. Simulation results establish the superior performance of proposed '4-Bit 4-Tube CNFET-based ALU' in terms of propagation delay (tp) (9.04×), PWR (1.68×), PDP (15.09×) and EDP (136.42×). The exposition establishes that the idea of using a 'CNFET-based 3-bit MCML parity checker' to design a new ALU circuit, i.e., '4-Bit 4-Tube CNFET-based ALU' would provide a gigantic horizon for a design engineer. [ABSTRACT FROM AUTHOR]

MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for competent and novel substances to overcome the shortcoming of existing silicon. The future technology should be capable to deliver fast response, low power operation, scalable to reduced dimensions, and strong towards process variations. Carbon nanotube based technology (CNFET) is one of the reliable and competent alternative because it has most of these desired features and similar operating principle as that of CMOS. And hence, this research article focuses on a relative evaluation of CMOS and CNFET version of 3 bit parity checker at 16-nm technology nodes. The CNFET based 3 bit parity checker is faster (9.75×), it offers improvement in power dissipation (11.93×), improvement in PDP (116.39×), improvement in EDP (1135.76×) compared to CMOS counterpart. Scaling down the device emerges with a challenge of variability, just as power, delay and area, variability also has an impact on performance of the circuit. Technology scaling has significant consequences such as wider variation. This research article also presents variability analysis, in terms of delay (tp) and power-delay product (PDP) for the proposed CNFET based MCML 3 bit Parity checker circuit. Extensive simulation using 16-nm technology node are carried out by loading two nominal copies of 'CNFET based MCML 3 bit Parity checker' (Circuit under Test) at either ends—input and output. This simulation framework supports the high level integration where stand alone operation has no application in the industry. The intent of this research is to investigate the circuit with minimal variability to propagation delay and PDP. The proposed 'CNFET based MCML 3 bit parity checker' exhibits improvement in delay (14.01×) and improvement in PDP (242.1×) variability as compared to CMOS counterpart. Thus, the CNFET based implementation emerges out as a robust circuit showing narrower spread in variability analysis against applied VDD. [ABSTRACT FROM AUTHOR]

Prodigious demand for fast performance-ultra low power electronic devices has insinuated the discovery of circuit style that promises reduced propagation delay ( t ), as well as low power dissipation ( PWR). MOS current mode logic (MCML) style has emerged as a promising logic style that offers high speed of operation at the expense of acceptable power dissipation. This paper proposes a MCML full adder which employs a load controller circuit. It compares MCML full adder with hybrid-CMOS full adder in terms of various design metrics in superthreshold as well as subthreshold regions. MCML topology with load controller offers a high speed of operation and low power dissipation in superthreshold region. Same circuit arrangement, when operated in subthreshold region also delivers higher operating speed with ultralow power dissipation compared to its hybrid-CMOS counterpart. Power dissipation analysis established MCML based full adder more robust compared to its hybrid-CMOS counterpart. In particular, MCML full adder design achieves 3.77× (2.38×) improvement in propagation delay, 10.43× (3.45×) improvement in average power dissipation, 39.43× (8.21×) lower power-delay product (PDP) and 149.07× (19.55×) improvement in energy-delay product (EDP) in superthreshold (subthreshold) regions of operation at 16-nm technology node. The above results are also validated using TSMC's industry standard 0.18-μm technology model parameters and a similar trend is observed in the design metrics of the MCML and hybrid-CMOS full adder circuits. In addition, noise performance of the above mentioned circuits is also carried out. It is observed that the noise induced by the hybrid-CMOS full adder is about 14× to that of the MCML full adder. [ABSTRACT FROM AUTHOR]

The role of major outer membrane protein (MOMP) variable regions in the interaction of chlamydiae and host cells has been evaluated and their role in neutralization of antibodies has been clearly demonstrated. There are also studies that delineate the contribution of these regions to the cell-mediated immune response of the host and suggest that serovar E elicits serovar-specific immune responses in infected humans. However, further studies with other serovars are required to confirm these findings and to elucidate the role and importance of serovar-specific responses of variable regions of MOMP in other serovars. We, therefore, performed a detailed analysis of the humoral and cellular immune responses against the serovar D-specific variable segments (VS) of MOMP in women infected with Chlamydia trachomatis. We found that VS4 elicits significantly higher responses (both humoral and cellular) than other VS peptides (VS1, VS2 and VS3). VS4 elicited significantly higher ( P < 0.0001) proliferative responses, interferon-gamma levels ( P < 0.0001) as well as higher prevalence ( P < 0.0001) of IgG antibodies against VS4 in serovar D-infected patients as compared to patients infected with other serovars, suggesting its role in serovar-specific immune responses. [ABSTRACT FROM AUTHOR]

The product packaging plays a crucial role in attracting consumers, persuading them to buy the product, and serving as a vehicle for brand communication. Around 73% of purchasing decisions are made at the point of sale. An enhanced appeal and attractiveness of the product make the selection process easier for consumers. Design and marketing are two major areas that are inextricably linked to each other. Good design distinguishes brands and makes products stand out from the crowd, instilling a certain perception in consumers' minds. Brands that meet the criteria for creating a lasting impression may dominate the market on a global scale in reality. The consumer must perceive the quality that the brand has built into the package, which may be accomplished through various design elements. Colour, shape, images, material, and package convenience are all important design elements in cosmetic branding. These elements are combined well together in a design, but there is a lack of a holistic approach in the design elements that are in line with the consumers' perspective. These aspects are highlighted in the review paper, which also looks at the importance of product packaging in cosmetics branding, and tries to highlight a few ways in which brands can minimize the gap between desired brand message and consumer perception about the brand., Competing Interests: Conflict of interestThe author has no conflict of interests to declare., (© The Author(s), under exclusive licence to Springer Nature Switzerland AG 2022.)