Search

This paper extends the driving-point signal-flow graphs to switched-capacitor (SC) circuits by introducing a new theoretical element: an auxiliary voltage source that transfers no charge. In contrast to existing SFG methods, our method has no restrictions as to what types of SC circuits can be analysed, it requires no equivalent circuits or tables, and it works with two-phase as well as multi-phase SC circuits of any complexity. Compared to charge-equation matrix methods, it requires more effort, but is better suited for hand analysis because it makes causal relationships visible. Three illustrative examples are given to show the efficiency of the method and present a few application hints: a voltage doubler, the standard SC integrator, and a four-phase circuit simulating an inductor. [ABSTRACT FROM AUTHOR]

The methods for switched-capacitor (SC) noise analysis published up to this date fall in two groups: one group contains methods suitable for analysis by hand that are not easily applicable to all SC circuits. The other group contains methods that are applicable to all SC circuits, but require matrix manipulations with a computer algebra tool. In this paper, we show a universally applicable hand-analysis method. The main reason why SC noise analysis is so difficult is that noise is sampled on many different capacitors, and when being sampled, its spectrum is aliased. The core idea of making analysis by hand possible is to use an intuitive rather than an algebraic method to derive the continuous-time noise spectra in the different phases. Our method combines charge-equation analysis for the discrete-time aspects with signal-flow-graph analysis for the continuous-time aspects of a circuit. We show in tutorial style how to apply it, and demonstrate that it is very useful for getting insight into SC circuits, deriving simplified expressions, and getting a good correspondence with behavioural simulations using SpectreRF. [ABSTRACT FROM AUTHOR]

This paper is a practical guide to building higher-order filters with single-amplifier biquadratic MOSFET–C sections. Theory, design guidelines, and measurement electronics are discussed by example of a 7th-order current-mode filter built to the specifications of a 1× DVD read channel filter. The 7th-order filter was fabricated with the double-poly 0.6-micron CMOS process by AMS. It is continuously tunable from 4.5 MHz up to 10 MHz, covers a chip area of only 0.24 mm2, and consumes 49 mW from a 3.3-V supply. The SNR at -40 dB of harmonic distortion is between 48 dB and 50 dB over the whole tuning range. The comparatively low power consumption and chip area could be achieved by using single-amplifier biquadratic building blocks implemented as MOSFET–C filters and generating the control voltage of the MOSFET resistors with an on-chip charge pump. The technique is, with a small loss of SNR, also applicable on fabrication processes where only gate-oxide capacitors are available. [ABSTRACT FROM AUTHOR]