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Reliability of Static Random Access Memories (SRAMs) is immensely affected by radiation induced soft errors. Multiple Cell Upsets (MCUs) are caused by these soft errors and this lead to data corruption in several SRAM cells. Error Correcting Codes are normally exploited to alleviate the effect of MCUs. Single Error Correction–Double Error Detection (SEC–DED) codes are not the appropriate preference against MCUs rather these codes are suitable for protecting SRAM cells against Single Cell Upset. Single Error Correction–Double Error Detection–Double Adjacent Error Correction (SEC–DED–DAEC) codes are more suitable due to increasing trends of single and double-adjacent errors in SRAM cells. In this paper, a new SEC–DED–DAEC code has been proposed which is proficient of correcting single and double-adjacent errors in SRAMs. Our newly proposed code has been termed as Single and Double-adjacent Error Correcting Code (SDECC). Proposed codecs have been designed by employing new parity check matrices for different word lengths which are frequently applied in memory. The mis-correction probability of proposed SDECC codes are up to 88.24% and 80.67% lesser for 2-random and 3-random bit errors respectively with respect to related existing designs. Proposed codecs have been replicated and synthesized in ASIC environment. It is observed that area and power consumption of the proposed codecs are reduced up to 8.93% and 21.47% compared to the recently published results respectively. [ABSTRACT FROM AUTHOR]

Importance of Error Correcting Codes (ECCs) is increasing rapidly for protecting memories from localized errors. These localized errors in memories are mainly due to radiation induced soft errors which corrupt data stored in a single cell or multiple cells of a memory. Initially, Single Error Correction (SEC) and Single Error Correction-Double Error Detection (SEC-DED) codes have been widely introduced to protect memories against soft errors. But with the incessant down scaling of technology node, the chances of multiple errors in memory cells are increasing day by day. The most common errors in multiple memory cells are the single error and double-adjacent errors. These errors are corrected by employing Single Error Correction- Double Adjacent Error Correction (SEC-DAEC) codes. But the major challenges in designing SEC-DAEC codes are higher decoding overheads and higher miscorrection rate. In this paper, the H-matrices for a new class of SEC-DAEC codes have been proposed to reduce the decoding overheads. The proposed codecs have been designed and synthesized in ASIC platform with suitable word lengths for memories. Both the theoretical and synthesis results for proposed codecs have been compared with recently published related works. These comparisons show that proposed (24, 16) codec requires a maximum of 1.38 times and 1.74 times lower area and delay respectively compared to other related codecs of same word length. Also the proposed 64-bit codec consumes a highest of 2.75 times lesser power with respect to existing 64-bit codecs. Thus the proposed codecs can be employed in memories for correcting single and double-adjacent errors with improved area, delay and power requirements. [ABSTRACT FROM AUTHOR]

Mostly random and adjacent error correcting codes are used to protect stored data in SRAMs against multiple bit upsets (MBUs). These MBUs caused by radiation are an important issue related to the reliability of static random access memories (SRAMs). As a result, multiple adjacent bits of a memory are distorted and valuable information is lost. To mitigate these problems, multi-bit adjacent error correcting codes are preferable in SRAM. In this paper, single error correction-double error detection-double adjacent error correction (SEC-DED-DAEC) codes are proposed. The performances of the proposed SEC-DED-DAEC codes are observed in terms of area and delay. Theoretical area overhead of proposed codes is at most 49.98% lower compared to the related design. Also the proposed design has around 28.79% lesser critical path delay compared to existing design. The best improvement achieved in terms of number of look-up table (LUT) and delay are 22.69 and 29.98% respectively compared to other existing codes in FPGA platform. The proposed codes can be used in embedded SRAM applications. [ABSTRACT FROM AUTHOR]