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Base stations have been built from ASICs, DSP processors, or FPGAs. This paper studies the feasibility of building wireless base stations from commercial graphics processing units (GPUs). GPUs are attractive because they are widely used massively parallel devices that can be programmed in a high level language. Base station workloads are highly parallel, making GPUs a potential candidate for a cost effective programmable solution. In this work, we develop parallel implementations of key kernels to evaluate the merits of using GPUs as the baseband signal processor. We also study the mapping method of key kernels onto a multi-GPU system to minimize the number of required GPUs and the overall subframe processing latency. Our results show that the baseband subsystem in an LTE base station, which supports ≤150 Mbps peak data rate, can be built with up to four NVIDIA GTX 680 GPUs and commercial motherboards. We also show that the digital processing subsystem for a 75 Mbps LTE base station can be built using two NVIDIA GTX 680 GPUs with power consumption of 188 W. [ABSTRACT FROM AUTHOR]

In this paper, we apply discrete-event system techniques to model and analyze the execution of concurrent software. The problem of interest is deadlock avoidance in shared-memory multithreaded programs. We employ Petri nets to systematically model multithreaded programs with lock acquisition and release operations. We define a new class of Petri nets, called Gadara nets, that arises from this modeling process. We investigate a set of important properties of Gadara nets, such as liveness, reversibility, and linear separability. We propose efficient algorithms for the verification of liveness of Gadara nets, and report experimental results on their performance. We also present modeling examples of real-world programs. The results in this paper lay the foundations for the development of effective control synthesis algorithms for Gadara nets. [ABSTRACT FROM AUTHOR]

Commercial and research work in the field of software defined radio (SDR) has produced designs which have been able to deliver the efficiency and computational power needed to process 3G wireless technologies. Though efficient 3G processing has been achieved by these designs, next generation 4G SDR technology requires 10-1000x more computational performance but limits the power budget increase to 2-5x. In this paper, we present a breakdown of the major 4G kernels and analyze two methods of increasing performance and reducing power consumption. Specifically, we consider the effect of SIMD width and reduction in number of register file accesses on the performance and energy consumption of a SDR architecture, SODA. We show that by increasing SIMD width we can gain almost 2-8x performance increase while increasing total energy used by 1-2x for different SIMD widths. We also show that by reducing SIMD register accesses we can reduce the total energy used by 5-20% for the 4G kernels. [ABSTRACT FROM AUTHOR]

General-purpose processors are often incapable of achieving the challenging cost, performance, and power demands of high-performance applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a processor for a particular application. The processor is extended with hardware in the form of a set of custom function units and instruction set extensions. To effectively identify opportunities for creating custom hardware, a dataflow graph design space exploration engine heuristically identifies candidate computation subgraphs without artificially constraining their size or shape. The engine combines estimates of performance gain, cost, and inherent limitations of the processor to grow candidate graphs in profitable directions while pruning unprofitable paths. This paper describes the dataflow graph exploration engine and evaluates its effectiveness across a set of embedded applications. [ABSTRACT FROM AUTHOR]

The PICO-NPA system automatically synthesizes nonprogrammable accelerators (NPAs) to be used as co-processors for functions expressed as loop nests in C. The NPAs it generates consist of a synchronous array of one or more customized processor datapaths, their controller, local memory, and interfaces. The user, or a design space exploration tool that is a part of the full PICO system, identifies within the application a loop nest to be implemented as an NPA, and indicates the performance required of the NPA by specifying the number of processors and the number of machine cycles that each processor uses per iteration of the inner loop. PICO-NPA emits synthesizable HDL that defines the accelerator at the register transfer level (RTL). The system also modifies the user's application software to make use of the generated accelerator. The main objective of PICO-NPA is to reduce design cost and time, without significantly reducing design quality. Design of an NPA and its support software typically requires one or two weeks using PICO-NPA, which is a many-fold improvement over the industry norm. In addition, PICO-NPA can readily generate a wide-range of implementations with scalable performance from a single specification. In experimental comparison of NPAs of equivalent throughput, PICO-NPA designs are slightly more costly than hand-designed accelerators. Logic synthesis and place-and-route have been performed successfully on PICO-NPA designs, which have achieved high clock rates. [ABSTRACT FROM AUTHOR]

A compiler for VLIW and superscalar processors must expose sufficient instruction-level parallelism (ILP) to effectively utilize the parallel hardware. However, ILP within basic blocks is extremely limited for control-intensive programs. We have developed a set of techniques for exploiting ILP across basic block boundaries. These techniques are based on a novel structure called the superblock. The superblock enables the optimizer and scheduler to extract more ILP along the important execution paths by systematically removing constraints due to the unimportant paths. Superblock optimization and scheduling have been implemented in the IMPACT-I compiler. This implementation gives us a unique opportunity to fully understand the issues involved in incorporating these techniques into a real compiler. Superblock optimizations and scheduling are shown to be useful while taking into account a variety of architectural features. [ABSTRACT FROM AUTHOR]