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This paper presents an algorithm based approach for TFET (Tunnel Field Effect Transistor) design. A numerous number of meta-heuristic algorithms have been used to procure the best device dimension for a Si–Ge (Silicon–Germanium) pocket n-TFET. The foremost important task is to find an alternative to hit and trails based device optimization and thereby improve the device performance by using those techniques. The algorithm based approach requires an objective function. The surface potential based models efficiently represents the device physical properties, thus surface potential based model is used as an objective function. The impact of the channel length, of the Si–Ge layer and device thickness, as well as of oxide thickness are studied by considering them as design variables. The design process involves simulating and validating the obtained dimensions in Technology Computer Aided Design (TCAD). State of art techniques are being outperformed by this algorithmic approach and out of all applied algorithms the Human Behavior Particle Swarm Optimization algorithm (HBPSO) is more accurate. An ON-current of 4.8 × 10–4 A and OFF-current of 4.8 × 10–12 A is achieved by optimizing the structure. [ABSTRACT FROM AUTHOR]

In the present era, with the advancement of various non-conventional devices, hardware components dimensions are shrinking to great extent. Among those, significant part of researchers focus is drawn by Tunnel Field Effect Transistors (TFETs), because of their fundamental attribute of carriers conduction through built-in tunnelling mechanism. In this work, an asymmetric gate Tunnel Field Effect Transistor (TFET) is reported and discussed. This device structure relies on Asymmetric Dual Material Double Gate Tunnel Field Effect Transistor (ADMDG TFET) with reduced oxide thickness of 0.5 nm and optimised metal work function used at the gate terminal of the proposed TFET. For the performance analysis of such a short channel device, the relevant parameters, like threshold voltage, electric field, drain current, surface potential, Ion, Ioff and Subthreshold Swing (SS), have been considered. The proposed structure is simulated by means of the 2-D Sentaurus TCAD tool. The results report significantly low OFF-state current (Ioff), considerably improved ON-state current (Ion), and enhanced SS. [ABSTRACT FROM AUTHOR]

The complex process of semiconductor device design requires precise models and efficient optimizers. This article puts forward an Asymmetrical Hetero-Dielectric (AHD) Triple Material Gate (TMG) n-type Junctionless Tunnel Field Effect Transistor (JL-TFET). A higher gate control is achieved by using triple material in control gate and hetero-dielectric oxide, which results in high ON current and low leakage. The surface potential based model for the proposed structure is derived by analytically solving 2-D Poisson's equation with hetero-dielectric gate oxide. This work also adopts intelligent techniques for extraction of optimal model parameters by using the derived mathematical model for the proposed JLTFET structure. The optimization technique used in this work combines the advantage of Particle Swarm Optimization (PSO) algorithm and Differential Evolution (DE) algorithm. A comparison with the conventional design process reflects that the use of optimization technique provides a novel approach to tune the process parameters. This technique outperforms the state of art design techniques and provides best accuracy along with exceptional computational efficiency. A current ratio of 1.25 × 1010 A and Point Subthreshold Swing (SS) values of 9 mV/dec and average SS of 48 mV/dec is achieved by optimizing the proposed structure. [ABSTRACT FROM AUTHOR]

The performance of TFET is limited by low ON state tunnel current. This paper introduces a novel p-channel tunnel field effect transistor (TFET) which incorporates a hetero-structure channel layer made of Si/intrinsic—SiGe. Also, tensile strained Si1−xGex p-type channel is used which enhances the device characteristics, where x is the Ge-mole fraction. The proposed structure exhibits a very small subthreshold swing and a high ON–OFF current ratio. The device characteristics are improved on the basis of theoretical principles and simulation results. The structure is improvised to achieve higher values for ON-current as compared to previously reported structures in literature. The average value of subthreshold swing and ION-current are found to be 59 mV/dec and 10−5 A/µm. [ABSTRACT FROM AUTHOR]

A new technique is proposed herein for the design and optimization of double-gate heteromaterial tunnel field-effect transistors (FETs). The presented approach determines the optimum device dimensions, using a reference analytical model of the surface potential as an objective function. Many high-performance evolutionary optimization algorithms have been applied to determine optimum dimensions at reduced computational cost and complexity. A comparison of all these algorithms reveals particle swarm optimization to be the most suitable in terms of achieving an optimum surface potential at higher convergence speed. The optimized values are validated against technology computer-aided design (TCAD) simulation results, revealing acceptable values for the ON-current, and an OFF-current of 4.8 × 10−15 A in accordance with International Technology Roadmap for Semiconductor (ITRS) 2014 requirements. The subthreshold slope is found to be 45 mV/dec. The algorithm dynamically fixes the lengths of the source, channel, and drain junctions, device thickness, etc. The automated determination of these parameters can effectively improve the computational complexity while providing accurate designs for tunnel field-effect transistors. [ABSTRACT FROM AUTHOR]