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The aim of this paper is to present a flexible and open-source multi-scale simulation software which has been developed by the Device Modelling Group at the University of Glasgow to study the charge transport in contemporary ultra-scaled Nano-CMOS devices. The name of this new simulation environment is Nano-electronic Simulation Software (NESS). Overall NESS is designed to be flexible, easy to use and extendable. Its main two modules are the structure generator and the numerical solvers module. The structure generator creates the geometry of the devices, defines the materials in each region of the simulation domain and includes eventually sources of statistical variability. The charge transport models and corresponding equations are implemented within the numerical solvers module and solved self-consistently with Poisson equation. Currently, NESS contains a drift–diffusion, Kubo–Greenwood, and non-equilibrium Green's function (NEGF) solvers. The NEGF solver is the most important transport solver in the current version of NESS. Therefore, this paper is primarily focused on the description of the NEGF methodology and theory. It also provides comparison with the rest of the transport solvers implemented in NESS. The NEGF module in NESS can solve transport problems in the ballistic limit or including electron–phonon scattering. It also contains the Flietner model to compute the band-to-band tunneling current in heterostructures with a direct band gap. Both the structure generator and solvers are linked in NESS to supporting modules such as effective mass extractor and materials database. Simulation results are outputted in text or vtk format in order to be easily visualized and analyzed using 2D and 3D plots. The ultimate goal is for NESS to become open-source, flexible and easy to use TCAD simulation environment which can be used by researchers in both academia and industry and will facilitate collaborative software development. [ABSTRACT FROM AUTHOR]

In this paper, we focus on the TCAD simulation and accurate compact model extraction of the time evolution of statistical variability in conventional (bulk) CMOS transistors, due to bias temperature instability (BTI). The 25-nm physical gate length MOSFETs, typical for 20 nm bulk CMOS technology, are used as test-bed transistors to illustrate our approach. Statistical physical simulations of fresh devices and devices at initial, middle and final stages of BTI degradation are performed and the corresponding nominal and statistical compact models are extracted using a two-stage extraction strategy. The extracted compact models not only accurately capture time evolution of the statistical distribution of the key MOSFET figures of merit, but also the complex correlations between them. An excellent agreement with the original physical TCAD simulation results provides a high degree of confidence that the extracted compact models deliver accurate representation of the operation of each device for the purposes of reliable circuit simulation and verification. [ABSTRACT FROM AUTHOR]

Flash memory devices-that is, non-volatile computer storage media that can be electrically erased and reprogrammed-are vital for portable electronics, but the scaling down of metal-oxide-semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory, but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory, there are a number of significant barriers to the realization of devices using conventional MOS technologies. Here we show that core-shell polyoxometalate (POM) molecules can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core-shell POM clusters, we show, at both the molecular and device level, that embedding [(Se(iv)O3)2]4− as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [Se(v)2O6]2− moiety containing a {Se(v)-Se(v)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 5+ oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call 'write-once-erase'. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour. This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit. [ABSTRACT FROM AUTHOR]

Increasing impact of reliability on device and circuit performance requires new multiscale simulation solutions to improve the design flow from device to circuit, capable of simulating local atomic effects impact on circuits. Here we present an original framework starting from molecular dynamics and density functional theory (DFT) simulation to obtain an accurate description of oxide traps, that is included at the next stage into a dynamic reliability simulator, providing workload dependent Bias Temperature Instabilities (BTI) impact on devices, including reliability interactions with statistical variability. Finally simulation results of large samples are used to extract compact model libraries including the impact of oxide degradation on devices at a given time. As a final outcome we present a time dependent failure rate. [ABSTRACT FROM AUTHOR]

Evolvable Hardware has been a discipline for over 15 years. Its application has ranged from simple circuit design to antenna design. However, research in the field has often been criticised for not addressing real world problems. Intrinsic variability has been recognised as one of the major challenges facing the semiconductor industry. This paper describes an approach that optimises designs within a standard cell library by altering the transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to optimise the device widths within a standard cell. The designs are analysed using statistically enhanced transistor models (based on 3D-atomistic simulations) and statistical Spice simulations. The goal is to extract high-speed and low-power designs, which are more tolerant to the random fluctuations present in current and future technology nodes. The results show improvements in both the speed and power of the optimised standard cells and that the impact of threshold voltage variation is reduced. [ABSTRACT FROM AUTHOR]

With the scaling of field-effect transistors to the nanometre scale, it is well recognised that TCAD simulations of such devices need to account for quantum mechanical confinement effects. The most widely used method to incorporate quantum effects within classical and semi-classical simulators is via density gradient quantum corrections. Here we present our methodologies for including the density gradient method within our Drift-Diffusion and Monte Carlo simulators and highlight some of the additional benefits that this provides when dealing with the charge associated with random discrete dopants. [ABSTRACT FROM AUTHOR]

In this paper, we present models and tools developed and used by the Device Modelling Group at the University of Glasgow to study statistical variability introduced by the discreteness of charge and matter in contemporary and future Nano-CMOS transistors. The models and tools, based on Drift-Diffusion (DD), Monte Carlo (MC) and Non-Equilibrium Green’s Function (NEGF) techniques, are encapsulated in the Glasgow 3D statistical ‘atomistic’ device simulator. The simulator can handle most of the known sources of statistical variability including Random Discrete Dopants (RDD), Line Edge Roughness (LER), Thickness Fluctuations in the Oxide (OTF) and Body (BTF), granularity of the Poly-Silicon (PSG), Metal Gate (MGG) and High- κ (HKG), and oxide trapped charges (OTC). The results of the statistical simulations are verified with respect to measurements carried out on fabricated devices. Predictions about the magnitude of the statistical variability in future generations of nano-CMOS devices are also presented. [ABSTRACT FROM AUTHOR]

It is expected that published results from drift diffusion simulation of oxide thickness fluctuations in nano-scale devices underestimates the true intrinsic device parameter variation by neglecting local variations in surface roughness scattering. We present initial results from 3D ‘bulk’ Monte Carlo simulation including an ab initio treatment of surface roughness scattering capable of capturing such transport variation. The scattering is included directly through the real space propagation of carriers in the fluctuating potential associated with a randomly generated interface. We apply this approach to simulate inversion layer mobility in order to validate the model before its possible application in device variability simulations. Qualitative agreement is found with universal mobility data and avenues for possible calibration of surface and simulation parameters are highlighted. [ABSTRACT FROM AUTHOR]

End of the roadmap integrated circuit interconnects suffer from capacitance variability due to line edge roughness (LER), significantly impacting overall circuit performance. We forecast the capacitance variability of short range interconnects with realistic line edge roughness at the upcoming 45, 32, and 22 nm technology nodes using a fast TCAD capacitance tool. Capacitance variability is layout sensitive and worsens with reduction in feature size, and together with the increasing device variability requires inclusion in statistical models of standard cells from the 45 nm node onwards. If LER does not improve then, for example, by the 22 nm node, short parallel lines on metal 1 are predicted to have 12% variability and, depending on layout, SRAM bit line capacitance 7% variability. [ABSTRACT FROM AUTHOR]

Monte Carlo remains an effective simulations methodology for the study of MOSFET devices well into the decananometre regime as it captures non-equilibrium and quasi-ballistic transport. The inclusion of quantum corrections further extends the usefulness of this technique without adding significant computational cost. In this paper we examine the impact of boundary conditions at the Ohmic contacts when Density Gradient based quantum corrections are implemented in a 3D Monte Carlo simulator. We show that Neumann boundary conditions lead to more stable and physically correct simulation results compared to the traditional use of Dirichlet boundary conditions. [ABSTRACT FROM AUTHOR]

Accuracy of timing in circuits and systems using nanoscale transistors is crucial and is dependent, to first order, on the capacitances of the load transistors. It is accepted that variation in parameters will be intrinsic to such devices due to, among other factors, the discrete nature of the doping. It is likely that one such parameter exhibiting variation will be capacitance. Here we investigate, using 3-dimensional simulation, the fluctuation in gate and drain capacitance in a 30 nm MOSFET due to random discrete doping. [ABSTRACT FROM AUTHOR]

The use of high-κ material in the gate-stack of future nano-CMOS devices presents a number of technological issues which may degrade the device performance and also lead to parameter fluctuations between devices. The polycrystalline nature of many high-κ materials may lead to non-uniformity in the dielectric properties across the oxide film, resulting in fluctuations in important device parameters such as the threshold voltage. Here, the effect of random grain orientation of the high-κ dielectric in the gate stack on parameter fluctuations in the corresponding nanoscale MOSFETs is investigated. [ABSTRACT FROM AUTHOR]

The magnitude of fractional current variation in ultra-small (30 nm channel length) MOSFETs due to single charge trapping-detrapping events at any position within the gate dielectric is studied using numerical simulation. These random telegraph signals in the drain current indicate the amplitude of low frequency MOSFET noise. Simulations are performed for realistic devices with poly-silicon gates subject to poly-silicon depletion, and for both SiO2 and HfO2 as dielectric materials. [ABSTRACT FROM AUTHOR]

A statistical study of intrinsic parameter fluctuations due to discrete random dopants in well scaled conventional MOSFETs is presented, using 3D simulations with quantum corrections to resolve the effects of individual dopants. The scaled devices are based on a realistic 35 nm gate length MOSFET. A significant increase in the parameter fluctuations in the devices scaled below 20 nm gate lengths have been observed. [ABSTRACT FROM AUTHOR]

We investigate the linearity performance of dual-gate and fully-depleted silicon-on-insulator MOSFETs through use of 2D computer simulations, which take into account quantum mechanical considerations and non-equilibrium transport effects. We show that DG MOSFET is superior not only in terms of gm /Id characteristics, central to analog performance, but also in terms of linearity performance, by up to 5 dBm, in most operating conditions. Linearity figures of devices considered in this work range from −10 to −20 dBm, which answer the needs of mobile communication standards currently in use. We also observe that, when properly scaled, bulk MOSFETs display competitive analog performance and have third-order intercept figures very similar to SOI device. We can identify, through simulation experiments, that quantum mechanical effects have positive impact on linearity, while non-equilibrium conditions lower linearity performance. With increasing drain bias, we find that linearity saturates at a moderately low voltage (∼1 V) in all devices. [ABSTRACT FROM AUTHOR]

In ‘atomistic’ device simulation the resolving of discrete charges onto a fine grained simulation mesh can lead to problems. The sharply resolved coulomb potential can cause simulation artefacts to appear in classical simulation environments using Boltzmann or Fermi-Dirac statistics. Various methods have been proposed in an effort to reduce or eliminate artefacts such as the trapping of mobile carriers in sharply resolved Coulomb wells, however they have met with limited success. In this paper we show an alternative approach for handling discrete charges in drift diffusion ‘atomistic’ simulations by properly introducing the related quantum mechanical effects using the Density Gradient formalism. This produces the desired effect of eliminating the trapping of mobile charge in heavily doped regions of the device. [ABSTRACT FROM AUTHOR]

Scaling of conventional MOSFETs to channel lengths of 20 nm and below will require channel doping in the range of 1019 cm−3. At such doping concentrations ionised impurity scattering may start to dominate over interface roughness scattering within the channel. Additionally, discrete doping variations, both in number and position, will become increasingly important in such small devices resulting in mobility variations from device to device. Such mobility variations will be in addition to the random dopant induced fluctuations due to the electrostatics. Here we report results from 3-D Ensemble Monte Carlo simulations that include ab-initio ionised impurity scattering, and has been developed to investigate mobility variations in small volumes comparable to the channel region of nano-scale MOSFETs. [ABSTRACT FROM AUTHOR]

We present an efficient simulation approach to study the universal mobility behaviour in Si MOS structures with random Si/SiO2 interfaces. Our approach is based on 3D Brownian dynamics in devices with realistic Si/SiO2 interfaces reconstructed from a Gaussian or exponential correlation function. The carrier-interface roughness scattering is treated ab-initio in our simulations and it results in correct velocity and real space distributions. The method is efficient and capable of 3D simulation of the interface roughness limited mobility in small MOSFETs in a statistical manner. After a careful calibration procedure, we reproduce the effective field dependence of interface mobility for μBulk = 1100 cm2/Vs using a random interface with single atomic steps and a correlation length of 6 nm. [ABSTRACT FROM AUTHOR]

The double gate MOSFET architecture has been proposed as a possible solution to allow the scaling of MOSFETs to the sub-30 nm regime, particularly due to its inherent resistance to short-channel effects. The use of lightly doped, or even undoped, channels means that such devices should be inherently resistant to random dopant induced fluctuations which will be one of the major obstacles to MOSFET scaling towards the end of the Si Roadmap. Random dopants within the channel are not, however, the only source of intrinsic fluctuations within MOSFETs at this scale. In this paper we investigate the impact of discrete dopants in the source and drain, individual charges within the active region and line edge roughness on the intrinsic parameter fluctuations in double gate MOSFETs. [ABSTRACT FROM AUTHOR]