Search

This article presents an exact mid-band gain-expression for the CMOS operational-transconductance-amplifier (OTA) with low-voltage-cascode-current-mirror (LVCCM) load. Its small-signal analysis is not available in any CMOS text-book or other published sources/articles. A simplified and innovative technique is employed in performing this analysis with an in depth tutorial flavor. It shows that the derived mid-band gain of the CMOS OTA with LVCCM load is significantly more accurate than that obtained using the highly approximate classical gain-expression of the OTA employing a standard cascode-current-mirror equivalence which may be used in textbooks and other articles. Circuit simulations employing the 180-nm and 65-nm TSMC CMOS process technologies has been performed to indicate the progressively higher accuracy of the derived exact gain-expression for the LVCCM loaded OTA with technology scaling. This new analysis indicates an additional degree of freedom in tuning the gain of the OTA with LVCCM load using an additional transconductance parameter, gm5,6 of (M5, M6). A simplified expression is also deduced which provides an improvement over the classical approximate expression, due to the additional design insight and accuracy provided by this additional parameter while still being amenable to first order gain evaluation in a simplified way. The presented analysis is new and has not been reported before in open literature in any form. [ABSTRACT FROM AUTHOR]

This paper presents a new highly-simplified and elegant technique for the mid-band analysis of the source-follower which is extended for the analysis of gm-boosted source-follower and a non-ideal drain-loaded source-follower. The accurate analysis of the drain-loaded source-follower is then applied to the superposition-based accurate differential-gain analysis of a mismatched non-ideal differential-amplifier. This new generalized methodology provides a more comprehensive mismatch gain analysis of the non-ideal differential amplifier compared to that presently available in text-books and other published sources. The drain loaded source-follower was not presented before in any form, and, the new source-follower analysis and the analysis of the drain-loaded source-follower has not been reported before. The presented methodology renders unnecessary the need for the commonly employed "voltage-divider" form of the source-follower analysis and the associated circuit transformations/derivations to employ the voltage-divider form. A more accurate non-ideal differential-amplifier mismatch gain expression is attained by including an elegant drain-loaded source-follower analysis. Simulation results for the derivations are also provided. Comparison of Cadence AC simulation results for the mismatched differential amplifier (with various loads), with the previous and the newly presented analytical mismatch differential gain expressions confirm the superiority of the presented new generalized method. [ABSTRACT FROM AUTHOR]

This brief paper investigates the small-signal mid-band behavior of g -boosted follower-amplifiers which has not been explored previously and whose analysis is not available in text-books or any other source. Both g -boosted source follower and g -boosted emitter follower are considered in the mid-band analysis. A novel circuit/source transformation based 'pictorial' technique with progressively simplified circuit diagrams is employed for this mid-band analysis which generally eliminates the need for solving nodal or mesh equations. Final expression is often achieved by inspection of the simplified circuit without the need for circuit analysis. The paper also discusses g -boosted BiCMOS follower amplifier using substrate PNP device in a pure CMOS process. The analysis demonstrates that the unity gain accuracy of follower-amplifier can be considerably enhanced using the g -boosting technique without sacrificing bandwidth. [ABSTRACT FROM AUTHOR]

This article demonstrates simplified mid-band derivations for CMOS cascode and g -boosted cascode. While the cascode mid-band analysis is addressed in some textbooks through varying brief treatments, it is provided in this paper in a more in-depth and consolidated form using an easy approach. The detailed analysis of g -boosted cascode stage is mostly not available in textbooks (or any Web source) despite being an important analog building block in achieving gain enhancements. The mid-band analysis of this stage is made easy in this paper using a simple short circuit and inspection technique. There is no need to write or solve lengthy equations. Transformation of dependent current sources through ' opportunistic short circuits' is utilized often in achieving this ease in derivation. An interesting new concept of ' Algebraic ground' or ' Meta- ground' is introduced in relation to the g -boosted cascode. Some novel compound cascode stages with simplified approach to their mid-band derivations is also provided. Additional insight is also provided through a comparison of the cascode with the g -boosted cascode using the simplified models and derivations which is rarely available elsewhere. [ABSTRACT FROM AUTHOR]

In this paper an analog voltage-mode median filter, which operates on a 3 × 3 kernel is presented. The filter is implemented in a 0.35 μm CMOS technology. The proposed solution is based on voltage comparators and a bubble sort configuration. As a result, a fast (34 ns) time response with low power consumption (1.25 mW for 3.3 V) is achieved. The key advantage of the configuration is relatively high accuracy of signal processing, which allows the calculation of the median of signals with the difference in amplitude as small as 10 mV. This feature allows the application of the filter to vision systems with up to 7 bit equivalent resolution. The analytical and statistical analysis of the filter resolution, and analysis of its speed limitations are presented and compared to measurement results. Based on the achieved results, a set of guidelines for the filter design and optimisation is presented. [ABSTRACT FROM AUTHOR]

CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm. [ABSTRACT FROM AUTHOR]

Different design procedures to operate MOS translinear loops at low supply voltage are presented. They utilize innovative biasing strategies based on flipped voltage followers and floating batteries. An alternate topology based on coupled negative feedback loops is also introduced. Simulation and measurement results for various test chip prototypes validate the proposed techniques and allow comparison among them. [ABSTRACT FROM AUTHOR]

Two schemes for power-efficient gain-programmable V-I conversion based on class AB CMOS mirrors are introduced. The proposed topologies also allow for high-speed gain-programmable precision rectification. Experimental results from a test chip prototype in 0.5-μ m CMOS technology with ±1 V supplies are shown that validate the proposed circuits. [ABSTRACT FROM AUTHOR]

A compact, four-quadrant analog CMOS multiplier featuring wide dynamic range is presented. The capacitive voltage division obtained by the use of Floating-Gate MOS (FGMOS) transistors, and an accurate wide-swing current mirror based on active bootstrapping, allow a wide input range, low harmonic distortion, and high linearity. Simulation and measurement results for a 0.8 μm CMOS prototype demonstrate the validity of the proposed approach. [ABSTRACT FROM AUTHOR]

A novel first-order CMOS log-domain filter is presented. The internal voltage swing compression due to its instantaneous voltage companding nature, together with the use of Floating-Gate MOS transistors and its class AB differential topology, allows operation with a single 1 V supply while maintaining at the same time a large input range. Moreover, operation in weak inversion leads to very low power consumption. The filter can be tuned in more than one decade through its bias currents. Simulation and measurement results of an experimental prototype fabricated in a 0.8 μm CMOS technology demonstrate on silicon the feasibility of the proposed technique, which can be readily extended to higher-order filters. [ABSTRACT FROM AUTHOR]

The LINC transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. One crucial signal processing function of LINC is the signal component separator (SCS) which forms two constant-amplitude phase-modulated signals from the source signal. This paper presents an analog SCS chip implemented in a 0.35 μm CMOS process using a novel design based on the so-called voltage-translinear circuit principle. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that all output spurious levels some -55 dBc and -48 dBc could be obtained with a North American Digital Cellular (NADC) signal and an IS-95 signal, respectively. This implies a high degree of linearity. [ABSTRACT FROM AUTHOR]

In this paper, novel current-mode analog multiplier/divider circuits based on a pair of voltage-translinear loops are presented, featuring simplicity, precision and wide dynamic range. They are suitable for standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described. Experimental results are provided in order to verify their correct operation. [ABSTRACT FROM AUTHOR]

The power feedback technique is a simple and low cost linearization scheme suitable for consumer products such as hand sets. This paper presents a custom chip for linearization of RF power amplifiers using power feedback. The chip, implemented in a standard double-metal double-poly 0.6 μm CMOS process, operates with 3.3 V supply voltage and consumes 62 mW. When it was used to linearize a commercially available high efficiency RF power amplifier at 850 MHz, experimental results showed that out-of-band power at 30 kHz offset was reduced some 10 dB for a π/4-shifted DQPSK modulated North American digital cellular (NADC) signal. For the same level of adjacent channel interference (ACI), the efficiency was increased from 35% to 48%. [ABSTRACT FROM AUTHOR]

A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8μm CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about −118 dBc/Hz at 1 MHz from the carrier. [ABSTRACT FROM AUTHOR]