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This chapter introduces the concept of Physically Unclonable Functions (PUFs), their prospects for hardware security in IoT devices, and their interaction with traditional cryptography. Section 8.1 summarizes the background on PUFs, whereas Sect. 8.2 covers the metrics that are commonly used to evaluate PUF performance. Such metrics are used to comparatively review the state of the art on PUFs in Sect. 8.3. Section 8.4 covers vulnerabilities to malicious attacks attempting to clone or mimic a PUF. In the last section, we introduce the novel concept of PUF-enhanced cryptography as a promising direction aiming to merge PUFs and cryptography in a cohesive framework for IoT hardware-level security.

Since the invention of the first integrated circuit (IC) in 1958 and introduction of first standalone Central Processing Unit (CPU) in 1971, we witnessed and continue to observe the breathtaking advances in IC manufacturing, transistor density and architectural solutions. These advances fueled the imagination of developers so that we now have diverse application fields for integrated circuits. Till recently, we have intuitively trusted the chips to control our lives and processes, so we have huge amount of sensitive information processed in chips. However, nowadays, attacks are being launched increasingly for economic reasons by well-funded criminal organizations or for intelligence purposes to get access to secret and sensitive information. Moreover, the emergence of globalized and horizontal IC and semiconductor business model, mainly driven by cost savings, is requiring both designs and users re-asses their trust in hardware and even in the supply chain. In recent years many reports have appointed to these attacks on the electronic components and their supply chain. The semiconductor industry is today loosing over $4 billion a year due to these kind of attacks.  Hardware attacks and trust issues can be classified into the following classes:  IC data (assets) attacks: These are attacks that aim at retrieving the secret data of the IC; e.g., hacking a smart cart to get the secret key;  IC design (IP) attacks: These are attacks that aim at getting more information on the IC design in order to counterfeit it; e.g., perform reverse engineering on an IC or IP, steal and/or even claim the ownership;  IC functionality (tampering) attacks: these are attacks that target the alternation of the original function of the chip/system. For example, a chip ceases functioning or continues to operate but then in an impaired manner, a chip introducing corruption in the data, etc.  IC piracy: in these cases, fraudulent practices are used to illegally sell circuits to make "easy money". This class includes for example over-building of integrated circuit and re-packaging of used old circuits to re-sell as new ones. This seminar will present a survey of known attacks and practices in these 4 categories, as well as relevant research works and solutions. ** Presenter: Giorgio Di Natale received the PhD in Computer Engineering from Politecnico di Torino in Italy in 2003. He is currently a researcher (CR1) for the National Council of Scientific Research (CNRS). He has published articles spanning a broad range of diverse disciplines, including memory testing, fault tolerance, software implemented hardware fault tolerance and secure circuits. He is the action chair of the COST Action IC1204 (TRUDEVICE), senior member of the IEEE and chair of the European group of the Test Technology Technical Council (TTTC) of IEEE Computer Society.

Over time, hardware designs have constantly grown in complexity and modern platforms involve multiple interconnected hardware components. During the last decade, several vulnerability disclosures have proven that trust in hardware can be misplaced. In this article, we give a formal definition of Hardware-based Security Enforcement (HSE) mechanisms, a class of security enforcement mechanisms such that a software component relies on the underlying hardware platform to enforce a security policy. We then model a subset of a x86-based hardware platform specifications and we prove the soundness of a realistic HSE mechanism within this model using Coq, a proof assistant system.

Hardware Trojans have become a major threat faced by most of the VLSI fabrication houses. This paper proposes a non-destructive method for Hardware Trojan detection. Since in many cases the golden chip is unavailable and hence voting technique is adopted.This paper is an extension of the weighed voting. A microcontroller based portable standalone system that will identify any malicious activity in a circuit was designed and implemented. This standalone system performs the weighed voting to detect any malicious activity of the Circuit under Test implemented in FPGA. The working of this standalone system was tested and validated by using ISCAS ‘85 Benchmark circuits implemented in Spartan 6 XC6SLX16 FPGA. The accuracy was around 93.93 % while testing the system. A novel hardware based solution for hardware Trojan detection is attempted in this work.