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Microelectrode-Arrays (MEAs) allow neural recording of thousands of neurons/mm2 by sensing: Extracellular Action Potentials (EAP) and Local Field Potentials (LFP). MEAs arrange several recording sites (or pixels) in a spatial grid/matrix, planarly and capacitively coupled with in-vitro cell cultures (growth above the chip surface) and/or integrated in electrocorticography grids. This paper focuses on Electrolyte-Oxide (C)MOS Field-Effect-Transistors MEAs for cell-level recording. In this type of biosensors, each single row of the matrix is composed of N planar metal electrodes and is scanned synchronously and regularly for N clock cycles, adopting Time-Division-Multiplexing (TDM) schemes. TDM approach generates an analogue output signal for each biosensor row, which includes in a single time track the information acquired by the N electrodes of the matrix. It is therefore of fundamental importance to estimate the noise power of the output signal of the single row because this power defines the minimum detectable threshold of the neuro-potential signal power. Noise in planar MEA is determined by the classical contributions of electronic noise (thermal and flicker, coming from both biological environment and semiconductor devices) and from the spurious corrupting signal due to multiplexing action (which behaves to all effects as a statistical noise signal following a Gaussian probability distribution). This paper presents the complete procedure for designing an (active) biosensor matrix/array (embedding the analog signal processing channels) as a function of a specific Noise Figure requirement (that measures the Signal-to-Noise-Ratio (SNR) degradation and thus is defined as the ratio between the biosensor array input SNR and the output SNR of the analog acquisition channel). This procedure is applied to a single row of the biosensor matrix, can be easily extended to 2D array, and allows to define all the design parameters (including electrode area, gain, bandwidth and noise power of the analog stages building the array) to obtain the specific Noise Figure.

This chapter targets low-power techniques for nanopower SAR ADCs with reference voltage generation. First of all, a 106nW 10b 80 kS/s SAR ADC with duty-cycled reference generation is presented, where a CMOS voltage reference, a duty-cycling block, and a LDO are integrated with the SAR ADC together. Furthermore, a low-power bidirectional comparator is utilized in the SAR ADC to reduce the power consumption. The reference-included SAR ADC achieves a FoM of 2.4fJ/conv.-step. Second, an energy-free DAC reset technique, “swap-to-reset,” is presented to deal with the large DAC reset energy in a SAR ADC, which is usually large compared with DAC conversion energy. In the prototype, the DAC energy consumption is reduced by one-third with “swap-to-reset” applied to the 2 MSBs. Finally, a low-power and area-efficient discrete-time reference driver is introduced. By calculating the energy consumption of each switching step, the DAC in a SAR ADC can be driven by a pre-charged decoupling capacitor compensated by a small auxiliary DAC. In the prototype, the SNDR/SFDR are improved by 2.7 dB/11.6 dB after enabling the 3b DAC compensation and the discrete-time reference driver only adds 10.8% and 10.1% to the power and chip area of the SAR ADC, respectively.

This book is based on the 18 tutorials presented during the 26th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, with specific contributions focusing on hybrid ADCs, smart sensors for the IoT, sub-1V and advanced-node analog circuit design. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

This paper presents a low power analog front-end circuit for a 3-axis MEMS capacitive accelerometer. The circuit includes an analog preamplifier to sense the signal coming from the sensor and a successive-approximation A/D converter. Power minimization is achieved by using a continuous-time preamplifier for realizing constant-charge capacitance-to-voltage conversion and a SAR A/D converter with split capacitive array. To cope with potentially large sensor leakage current we used a specific sensor biasing technique, that guarantees ac coupling above 0.1 Hz. The complete analog front-end circuit consumes 90 μW from a single 1.2-V power supply voltage, achieving 65.1 dB of SNR over a 4-kHz bandwidth and − 43. 4 dB of THD.

This book is based on the 18 tutorials presented during the 25th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of continuous-time sigma-delta modulators, automotive electronics, and power management. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

Amplifiers that need to drive heavy loads (low resistances and/or large capacitances) with good efficiency generally use a push-pull output stage. This intrinsically creates large open-loop distortion components that need to be compressed through feedback to insure high closed-loop linearity. Minimizing close loop residual distortion involves three steps that will be discussed in this chapter. Eliminate all open-loop source of distortion not intrinsic to the proper operation of the push pull structure. Second, choose the amplifier topology that gives the maximum close loop compression of the open-loop distortion components for a given bandwidth. Third, maximize the open-loop gain in the signal band and/or the unity gain bandwidth of the amplifier for a given topology while insuring stability in the presence of variable loads.

Analog filters are widely used in several kinds of integrated mixed-signal systems, since they are intrinsically needed for in-band signal selection, out-of-band noise rejection and anti-aliasing for the A-to-D (D-to-A) conversion. CMOS technological scaling down has already entered in nm-range scenario, leading to severe degradation of some of the most important MOS device performance for analog design. Among them, lower VDD/VTH ratio (supply voltage and threshold voltage, respectively), higher power consumption, and transistor intrinsic gain decreasing. On the other side the increasing MOS transistor transconductance (gm) and transition frequency (fT) enables tens of GHz applications, which take advantage of cheaper and smart CMOS processes. Specific continuous-time analog filters will be presented in this chapter, with the aim to introduce novel circuital topologies or optimizations and techniques suitable to mitigate the severe issues present in sub-90 nm CMOS technological nodes, and at the same time to exploit the opportunity of higher technological scaling-down.

This book is based on the 18 tutorials presented during the 22nd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including frequency reference, power management for systems-on-chip, and smart wireless interfaces. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development. Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia.