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Thermoplastic composite tapes are produced with a specific width, e.g. 300 or 600 mm. A common production method is first to slice the tape rolls into narrow tapes bands with a width of e.g. 50 mm. These narrow tapes are used for stacking operations. Upon using such a technology, it is necessary to combine several narrow tapes to end up with a single layer. The outer edges of the tape stack normally extrude beyond of the area needed for the part, meaning, a cutting operation is necessary, either right after the stacking or after the consolidation. A beneficial alternative approach starts with large cutouts from the rolls, which are obtained by efficient stamping. These cutouts cover as much area as possible in one piece. The idea is to use the full tape width, if possible. The cutouts are stored in automatized magazines and become stacked efficiently employing a pick-&-place approach. The use of image processing enables precise adjustment of the gaps and overlaps.

Artificially grown crystals have to be cut into wafers for further applications. The current wafering techniques are described with a major focus on the dominant multi-wire sawing method. After sawing the wafers may have to be further treated by grinding, lapping, polishing, and etching procedures. The requirements on the processes and wafer qualities depend on the material and the application. The most advanced techniques have been developed for silicon, which is the major material for photovoltaic and microelectronic applications. Multi-wire sawing and the subsequent processes use abrasive particles for material removal. The fine-tuning and optimization of the wafer processes require an understanding of the micromechanical interactions between abrasive particles and crystal. The current status of research and development will be described for the major methods and materials. Finally, a brief overview will be given for alternative wafer processing techniques.

Advanced HgCdTe infrared focal plane array (IRFPA) technology extends the ability of optoelectronic detection from single-band two-dimensional target imaging to multiple spectral three-dimensional imaging. It is developing continuously toward the direction to achieve higher resolution and more accurate identification. In terms of material technologies, the IRFPAs are requiring larger size wafers with higher performances and more complex structures in order to better detect multiple information from multiple objectives.

Silicon photonics will increasingly be adopted into commercial applications as the technology matures, and the demand for foundries is growing as companies search for photonic integrated chip (PIC) manufacturing support. The accessibility to foundries becomes a critical aspect for technology advancement and volume production. Foundry services for multi-project wafer (MPW) shuttles, customized process runs, and small volume production are discussed in this chapter. Results and challenges in setting up a CMOS manufacturing foundry line for silicon photonics research and development along with commercialization are also presented. The existing gap in the value chain presents an opportunity for foundries to be involved in a silicon photonics market that is primed for growth.

The research of pedestrian tracking algorithm in infrared image sequence is a curial part in video surveillance. But due to the special characteristics of infrared image, such as low contrast, fuzzy edge and unknown noises interference, the study of infrared pedestrian tracking algorithm becomes a great challenge. Spatio-temporal slice method is an effective analysis method considering both space and time. In view of the existing tracking methods based on spatio-temporal slice only considering horizontal slice analysis and usually with large amount of calculation, this paper proposes a novel tracking algorithm based on spatio-temporal slice trajectory analysis. The proposed algorithm uses multi-layer horizontal and vertical slices to obtain the complete trajectories in order to determine the information of target boundary and position, and then tracks the target in each frame of the infrared image sequence. The experimental results show that the algorithm has relatively high tracking accuracy at a fast computing speed. Moreover, it performs effectively in different infrared image sequences with various motion modes by single pedestrian from OTCBVS/05 Terravic Motion IR Database, namely, the algorithm has good robustness to some extent.

This chapter discusses two distinctive technology aspects related to the wafer itself. The first one is how to maintain a flatness of the layers built up on a wafer, despite the fact that a patterning step typically results in a characteristic surface topography. The second one is how to merge subcomponents built on separate wafers. While the semiconductor industry typically builds up the whole device (i.e., the integrated circuit—IC) on a single wafer, MEMS, with its unique micromachining approaches, quite often creates devices that involve two wafers. For solving these two challenges, two important enabling technologies are being utilized. The first one is chemical-mechanical planarization (CMP) to achieve a flat device surface. The second one is wafer bonding, allowing the merging of subcomponents of a system built up on separate wafers.

A defect detection vision system for the automatic optical inspection of wafer has been developed. For the successful defect detection, several thresholding methods are compared and the improved Otsu method is adopted so that it can handle both unimodal and bimodal distributions equally well. An automatic defect detection software was developed with the function of detection of ROI, fast thresholding. Finally each defect pattern in the wafer is classified and grouped into one of user-defined defect categories and more than 14 test wafers are tested for evaluation of detection and classification accuracy.

The artificial counting method for solar wafers cannot meet the production requirements because of the inefficiency, high breakage rate and inaccuracy. An accurate counting algorithm for solar wafers based on the texture feature was suggested. Firstly, Texture feature of acquired multilayer solar wafers was analyzed. Secondly, the edges of wafers region were located in the image by the grayscale distribution. Coordinates information of edges were used to correct the image and locate ROI(Region-of-Interest). The thresholding combining NiBlack with background correction was designed to obtain binary image. Noise was removed by particle Filter. The texture feature gap between pieces was improved by morphological method. Finally, counting was realized by self-adaption differential algorithms based on probability statistics. The result of experiments shows that the counting accuracy has achieved to 99.37%. The algorithm mentioned above is not only effective for the wafer images of low contrast, much noise and fuzzy boundaries, but also improves the efficiency and accuracy of the counting.

Thin supported elastic nano- or micrometric films are everywhere in our everyday life, and it is often of outmost importance for the quality of their function in a given application to be able to characterize precisely their mechanical properties. We show in the present review that this is however a quite difficult mechanical problem. We briefly present the successive contact mechanics models which have been elaborated to take into account the observed apparent increased rigidity of those elastic films when they are confined between the supporting solid and another solid (the indenter) used to squeeze them and deduce their mechanical properties from load versus deformation curves. We discuss the limitations of these models and put a special emphasis on the more recent one, by E. Barthel, which, based on a semi-analytical resolution of the contact mechanics equations, seems to correctly account for series of systematic experiments where micrometric elastomer films supported by a silicon wafer are characterized in a JKR test with microlenses of the same elastomer. We discuss in details why an important drawback of essentially all indentation type tests is the fact that they usually do not give access to the actual size of the contact between the probe and the tested film. A consequence is that adhesion contributions can hardly be incorporated in a correct manner. We then propose a new soft liquid probe test, in which the supported films are mechanically solicited not by a direct contact with another solid, but by the adjustable stress field resulting from the oscillating flow of a liquid intercalated between the films to be tested and a sphere which can be approached from the film down to a fraction of nanometers. We analyze the potentialities of this new test and show that it presents two main advantages compared to conventional solid–solid contact tests. First, the adhesion terms do not change during the test, as the solids are immersed into the liquid, and second, the amplitude of the stress field can be varied and perfectly controlled in an impressive wide range; thanks to the well-known validity of the Reynolds equations down to a few molecular sizes.

Realistic chips are composed of transistors, metal interconnects, and also substrates or basement materials that provide physical and electric supports to the chips. The popular silicon process starts from a nearly pure silicon wafer, which will be the foundation to grow active wells (p-wells and n-wells), and then in turn many layers of metal wires or interconnects. At frequency of several gigahertz, a substrate behaves mainly resistively. So, the substrate coupling which occurs mainly in the mixed-signal chip can be modeled with resistors connecting the contacts on the top surface of substrate. In this chapter, we introduce a direct boundary element method for substrate resistance extraction. With several novel techniques the method has high computational efficiency. It also demonstrates the versatility of handling substrate cases with lateral resistivity variations, which is beyond the ability of other methods.

The automated material handling system (AMHS) in semiconductor industry plays a vital role in reducing wafer cycle times and enhancing fabrication plant productivity. Vehicle allocation for the AMHS is a challenging task because of the complexity of the manufacturing process and the stochasticity introduced by the inherent variability of processing times. This situation is observed especially in 300 mm wafer fabrication plants where the AMHS comprises both interbay and intrabay systems that perform the timely deliveries. To address this issue, we use the optimal computing budget allocation (OCBA) and extend it by adding genetic algorithm (GA). Under this combined approached, the number of iterations of each alternative is determined by OCBA, and then the optimal solution in the domain of feasible solutions is found through GA. This research provides a useful reference for both scholars and practitioners seeking optimal allocation of lithographical resources and number of iterations using random parameters.

Nanostructures of piezoelectric materials are attractive building blocks for useful bioimplant devices such as self-powering nanogenerators and nano-biosensors. Yet, one of the most efficient piezo-nanomaterials - PbZr x Ti1 − x O3 (PZT) nanowires is difficult to synthesize without suffering from polycrystallinity or poor stoichiometric control. Current large-scale nanofabrication methods have been restricted by their complexity and cost, while bottom-up synthesis of nanowires has been limited in methods to assemble these structures at precisely-defined locations. Here, we report a novel fabrication method which requires only low resolution photolithography to generate ultra smooth, high performance PZT nanowires over wafer scales. These fabricated PZT nanomaterials also shows a biocompatible interface with living cells to offer a great potential for its applications in biomedicine such as self-powering implant devices and cellular biomechanical sensors.

With the continuous evolving of Liquid Crystal Display (LCD) panels and Integrate Circuits, conventional Anisotropic Conductive Film (ACF) has confronted with two paradoxical requirements: higher conductive particle density, while avoid serious aggregation. To solve this problem, a wafer level pretreatment technique, Particle on Bumps (POB), was proposed to renovate the usual Chip on Glass (COG) technology. Although we have demonstrated its feasibility and reliability, a fundamental route towards fully accomplishing the POB technique still needs to be paved out, that is the dispersing of conductive particles. Herein we introduced the method of Electrohydrodynamic Atomization (EHDA). EHDA is a technique which ultra-fine droplets can be induced due to electrical force. We build up a prototype apparatus for particle dispersing. With the help of high speed camera, we are able to verify certain behaviors and characteristics of different modes during the EHDA process. The deposition patterns generated under different spraying modes are observed and compared; the stable cone jet mode is therefore chosen as the operational state during our following deposition process. We investigate the connections between onset voltage and relevant spray parameters to optimize our EHDA configurations. By implementing the particle dispersing experiment via stable cone jet EHDA, we successfully obtained a pattern with high densely and uniformly distributed particles.

Stainless steel (SUS) has been used in many industrial fields such as bio and medical parts. Especially, implanted medical device (IMD) has been widely researched for enhancing a human life from biological treatment using those devices. These medical devices require some essential requirements, such as biocompatible, non-toxic and human safety. For these reason, many researchers have been suggest a method of surface treatment to decrease a biological damages due to implanted in vivo. However, these proposed methods were had some disadvantages such as semi-permanent and require additional processes. To overcome these disadvantages, our research proposes a surface texturing method that is anodic oxidation based on electro-chemical reaction. Firstly, 1μm aluminum thin layer was deposited on the 4inch SUS-316L wafer. At this point, for the comparison of SUS-316L wafer with different surface roughness conditions, we have prepared polished and unpolished surface wafer. Using suggested method, porous aluminum oxide layer was formed and then we have removed oxide layer using alumina chemical etchant. Finally, we have fabricated various shapes of irregular nano/micro dimple structures with 100nm to 50μm according to surface roughness conditions.

Building high-performance silicon CMOS or III/V devices requires many structural process steps, where a physical layer (dielectric, epitaxial semiconductor, gate electrode, or metal contact) is first deposited across the wafer and then partially removed by a masked or blanket etch process. Whenever possible, the deposition and etch processes are verified by a thickness metrology step. Typically, a latest-generation CMOS process flow contains about 100 thickness measurements, at least during the development of the technology. The metrology method of choice in the semiconductor industry is spectroscopic ellipsometry, because it is fast, non-destructive, and capable of measuring product wafers in small areas (30–50 \(\upmu {}\)m beam diameter) set aside in the scribe grid. This chapter will describe several typical applications of ellipsometry in CMOS and III/V device manufacturing and address capabilities and limitations and how future basic research on optical properties of materials can benefit the industry.

As the demand for ultra-clean areas in semiconductor fabrication has increased, the need for more efficient automated material handling system (AMHS) has become imperative. A diffusion tool is characterized by its long processing time of 6–12h, thus making it a form-batch manufacturing step. Out of necessity with this application, wafer lots are temporarily stored in stocker and are delivered to diffusion tools for processing when the Work-In-Process (WIP) level reaches 4–6 lots. As a result, diffusion tools wait for long wafer delivery time due to the current vehicle assignment method, thus greatly impacting transportation and production efficiency.

Thickness filed excitation and lateral filed excitation are the two kinds of excitation mode in piezoelectric resonator. In this chapter, shear mode FBAR excited by lateral filed is demonstrated in theory and experiment. Theoretical analysis of the Christoffel equation shows that a shear mode wave along thickness direct can be excited in c-axis-oriented ZnO or AlN with an in-plane excitation field oriented in any direction on the wafer. The electric characteristics of LFE resonators are deduced according to the potential solved from the plane wave formalism. A real LFE FBAR with solid mounted structure is fabricated and the performance is presented. The average Q-factor of the devices is approximately 520 in air, 408 in water and 313 in glycerol, respectively.

Micro-electro-mechanical systems (MEMS) technology ignites major breakthroughs in several research areas. Optics/photonics is one of these research fields impacted by MEMS techniques. Generally, microoptical elements with sizes ranging from a few microns to a few millimeters belong to the category of optical MEMS. They are inherently suited for cost effective wafer scale manufacturing as the processes are derived from the semiconductor industry. The advantages of applying microelectronics technology to silicon micromechanical devices were presented by Petersen in his classic paper, ‘Silicon as a Mechanical Material’[1].

An EIT method with planar electrode array has been proposed and a hand-held planar electrode system has developed. Based on a 3-dimentional finite element model, a modified weighted backprojection algorithm, which is back-projected along equipotential surfaces of the 3D electric filed, is used to reconstruct slice images of 3D conductivity distribution under electrode array. The electrical field distribution has been calculated and several slice images beneath the electrode plane have been reconstructed. The result showed that superficial object can be distinguished well, but image of deeper object needs to be improved sequentially in the future.

Photoluminescence and electroluminescence from amorphous silicon / crystalline silicon heterostructures is a measure of the radiative band-to-band recombination, described in terms of the quasi-Fermi level splitting according to Planck’s generalised law, and the experiments thus probe the excess carrier densities in the crystalline silicon. Depending on the layer structure of the investigated sample, the contact-less photoluminescence experiment allows the characterisation of precursor structures for solar cell optimisation and for the study of related physical aspects like interface recombination. Both photoluminescence and electroluminescence experiments can be applied to solar cells for which the luminescence yield, or more precisely the deduced quasi-Fermi level splitting, can be related to the open-circuit voltage of the device which itself is limited by factors like the interface recombination rate. The coverage of luminescence techniques is complemented here by an account of modulated photoluminescence, a variant of the experiment, which may be used for the lifetime determination in wafer structures. Numerical modelling provides additional insight into the physics of interface recombination and its impact on the quasi-Fermi level splitting and thus the luminescence yield and the open-circuit voltage.

In order to solve the problem of springback control difficulty in the bending process of stamping parts, on the base of the mechanism introduction of the springback, the algorithms of dynamic explicit and static implicit are analyzed. Dynamic explicit is used to analyze the forming process and its result is taken as the initial condition which is provided to the springback analysis with the algorithms of static implicit. Through the analysis of the calculation results, the thinning and springback is allowable and the forming process can meet production requirement.

Heterojunction (HJ) silicon solar cells use crystalline silicon wafers for both carrier transport and absorption, and amorphous and/or microcrystalline thin silicon layers for passivation and junction formation. The top electrode is comprised of a transparent conductive oxide (TCO) layer in combination with a metal grid. Heterojunction silicon solar cells have attracted a lot of attention because they can achieve high conversion efficiencies, up to 25%, while using low temperature processing, typically below 200 °C for the complete process. Low processing temperature allows handling of silicon wafers of less than 100 μm thick while maintaining a high yield.

The integration of organic light-emitting diodes (OLED) into semiconductor technology (CMOS) requires a protection, called encapsulation, which covers the OLED forming a barrier against the environment (oxygen, moisture, mechanical). The essential encapsulation technology has to be suitable for full-wafer production regarding low chip cost, fast throughput and accurate processing. A combination of thin-film and direct encapsulation might result in a proper protection for organic devices, containing the advantages of a good barrier, mechanical protection, easy extension with light-forming components and a pre-protection. Aligned adhesive wafer bonding technology is characterized for this hybrid encapsulation approach. A flow of fabrication steps is discussed, which builds up a sandwich of a CMOS wafer with the OLED and a cover glass wafer with color filter structures. This process flow manufactured an OLED microdisplay, which is implemented in a head-mounted display demonstrator.

To improve the performance of the multi-core processor, the slice is taken as the unit to design its architecture. The procedure is partitioned into the slices with similar sizes, such that the instructions in the slice can be executed in dataflow fashion. The instructions inside the slice are optimized according to the dataflow graph. The correctness of the proposed algorithm is validated with comparative analysis of the experimental results. The proposed algorithm of slice partition and optimization lays the foundation for establishing the whole tool chain of the multi-core compiler and programming the simulator.

The performance of crystalline silicon (c-Si) heterojunction (SHJ) solar cells critically depends on the properties of the deposited hydrogenated amorphous silicon (a-Si:H) films. Surface passivation is an important role they need to fulfill. Additionally, the a-Si:H films should also act as efficient emitter and back surface field (BSF). In this chapter, we focus on the electronic passivation properties of thea-Si:H/c-Si interface. First, relevant literature on c-Si surfaces is briefly reviewed, including the effect of hydrogenation of surface states. This is followed by a discussion of how electronic surface recombination is calculated and measured. Recombination is mainly determined by electronic gap-states. The precise nature of these states is discussed both for the c-Si surface and for the a-Si:H bulk. Next, the physical passivation mechanism of intrinsic a-Si:H is elucidated. It is concluded that it stems from chemical surface state passivation by hydrogen, similar to defect passivation in the a-Si:H bulk. For these films, it is also argued how epitaxial growth may detrimentally influence the passivation quality. For heterojunction devices this has its importance, as the deposition of device-grade a-Si:H is often very close to the transition to epitaxial growth. A following section focuses on the effect of doping of the amorphous films. Doping is principally expected to improve the passivation quality further, as it should give rise to additional field-effect passivation. Here, it is discussed why this is not necessarily the case, as doping is also linked to Fermi-level dependent Si–H bond rupture in the films. A compromise between doping and surface-passivation may be obtained by employing an intrinsic buffer layer between the doped film and the wafer. By using intrinsic buffer layers, values for the energy conversion efficiency as high as 23% were reported to date for SHJ devices.

This paper proposes a sampling technique to create a slice image with opacity to render the same volume. Our method is based on the particle-based rendering, which uses tiny particles as rendering primitives. In this research, three sampling methods are proposed for applying opacity: (1) Metropolis sampling of the whole plane, (2) Uniform sampling at each grid, (3) Metropolis sampling at each grid. The results show that the borderline is clearly shown in the low-opacity area using technique 2 and is clearly shown in the high-opacity area by using technique 3.

Nanolithography using Non-Contact Mode Atomic Force Microscopy (NCM-AFM) is a promising method for the manufacture of nanometer sized devices. Compact models which suggest nanopatterned oxide dots with Gaussian or Lorentzian profiles are implemented in a Monte Carlo simulator in a level set environment. An alternative to compact models is explored with a physics based Monte Carlo model, where the AFM tip is treated as a point charge and the silicon wafer as an infinite conducting plane. The strength of the generated electric field creates oxyions which accelerate towards the silicon surface and cause oxide growth and surface deformations. A physics based model is presented, generating an oxide dot based on the induced surface charge density. Comparisons to empirical models suggest that a Lorentzian profile is better suited to describe surface deformations when compared to the Gaussian profile.

Wafer lapping process affects product quality and competitiveness. Improving existing wafer lapping equipment, adding a automatically tuning system of slurry flow rate, wafer surface quality is improved, defective goods are decreased, and cost is saved.

In this work, we use a controlled oxidation of a mesoporous silicon substrate as a tool for extending and adjusting the Si lattice parameter to other materials such as SixGe1-x. Our approach involves four steps. First, a seed film is epitaxially grown on a single-crystal Si(100) wafer by Molecular Beam Epitaxy(MBE). Second, porosification is performed according to a standard electrochemical etching procedure but using a “two wafers technique”. Third, the porous part of the sample is oxidized at mild temperatures (300–500°C) in a dry O2 atmosphere, inducing a substantial in-plane expansion of the seed film. Fourth, an overgrowth by MBE of an epilayer is done to test the thus-obtained pseudosubstrate. The challenging task in this last step is to deoxidize the seed film surface at ~900°C without losing the strain induced by oxidation of the porous part of the sample.

In this work we continue our investigation on the heating effects in nano-scale FD-SOI devices using an in-house thermal particle-based device simulator. We focus on the current variations for FD-SOI devices with arbitrary crystallographic orientation and examine which crystallographic orientation gives better results from electrical and thermal point of view. Our simulation results demonstrate that one can obtain the lowest current degradation with (110) wafer orientation. The temperature of the hot-spot is the smallest for (110)-orientation as well.

The growth of epitaxial graphene on silicon carbide (SiC) is considered to be a viable route to the development of graphene-based electronic devices. Consequently, much work has been done in the last few years on characterization of this material and on improving its growth and properties. This chapter is devoted to the growth and properties of epitaxial graphene on the hexagonal SiC(0001) surface. The properties of SiC are briefly summarized before the growth of graphene in ultrahigh vacuum (UHV) is described. Next, the electronic and structural properties of the so-called buffer layer are investigated before discussing the band structures of monolayer and bilayer graphene close to the K-point of the hexagonal Brillouin zone. Recent results indicate that growth of graphene in UHV is insufficient for obtaining electronic grade graphene layers. Instead, growth of graphene in Ar atmosphere has been suggested to lead to graphene synthesis on wafer scale and work on this topic is summarized. Then a brief description of transport properties of graphene on SiC(0001) is given. Finally, it will be shown how interface engineering of epitaxial graphene on SiC(0001) may be used to change the properties of the graphene layers.

We present a sampling technique that enables to explore transmission and reflection of fast electromagnetic pulses on a microstrip transmission line. Employing a minimally invasive optical sampling technique, temporal pulsed signals and the corresponding spectra are obtained for 20 GHz bandwidth.

Electrically pumped diode lasers emitting in the Near Infra-Red (NIR) spectral range (785-1400 nm) have been under intensive development for over 40 years, and are in wide commercial use in a range of applications. In an updated version of [08Wen1], we review here the semiconductor materials used to construct these devices and give an overview of peak performance published in recent articles. NIR diode lasers can be made using binary, ternary, quaternary, and quinternary compound alloys in the III-V material system. Materials with direct bandgaps of the required NIR emission wavelength can be currently grown with high quality typically on either InP or GaAs wafer substrates (other substrates such as InGaAs are also possible). Quantum-size effects can be used to adjust the emission wavelength through the use of nm-scale quantum well, wire, or dot structures. Such nm-scale structures allow in addition the use of moderate levels of crystal strain, which enables further modification in the emission wavelength. Figure 9.3.1 gives an overview of the 300 K bandgap of compound materials from the AlInGaAsSb material system as a function of lattice constant, as used in the majority of NIR diode lasers.

To effectively evaluate and analyze performance of cluster tools in semiconductor manufacturing, the paper presents a throughput model for parallel cluster tools .For developping this model, the timing diagram is applied to describe the usage of the chamber and robot in parallel processing of cluster tools. Finally, the theoretical model which indicates the relationship between the number of chamber, processing time, transport time, and throughtput is deduced. This model can analyze and computer the wafer period and the batch period fast and accurately.

This document is part of Subvolume B ‘Laser Systems’, Part 3 of Volume 1 ‘Laser Physics and Applications’ of Landolt-Bornstein Group VIII ‘Advanced Materials and Technologies’.

This study presents a novel microfabricated polymerase chain reaction (PCR) chip based on silicon. A microheater utilizing doped semiconductors as heating resistors and a temperature sensor made of Pt are integrated on the chip to make up a thermal module. The micro-stationary PCR chip is fabricated on a silicon wafer using photolithography, wet etching and ion implantation technology. The package is created without complex processes. Three types of configurations for the microheater are designed and simulated to analyze the temperature distribution by the finite element analysis so as to enhance the temperature uniformity in the reaction chamber. With this approach, the microheater is optimized. Finally, the simulation results are validated by infrared images from experiments.

Different ways to merge photonics devices on an electronic circuit with microelectronics tools on large-size wafers are addressed. This full integration enables improvement of either the functionalities of the electronic circuits or the miniaturization of optical functions. The above-integrated-circuit fabrication is preferred to a combined fabrication process, with two options ruled by thermal constraints. The high-temperature option is based on wafer bonding on an optical silicon-on-insulator module, and the low temperature option relies on the heterogeneous integration of III–V devices. Compatible with these options, several silicon-based building blocks have been developed, such as slightly etched rib waveguides with low propagation loss (0.1 dB/cm), crystalline and amorphous waveguides, efficient fiber couplers, a 42-GHz Ge integrated photodetector, and a 15-GHz Si modulator. Using molecular bonding of InP dice and processing in a microelectronics environment, InP laser sources have been achieved on silicon.

Market for Bulk GaN Crystals.- Development of the Bulk GaN Substrate Market.- Vapor Phase Growth Technology.- Hydride Vapor Phase Epitaxy of GaN.- Growth of Bulk GaN Crystals by HVPE on Single Crystalline GaN Seeds.- Freestanding GaN Wafers by Hydride Vapor Phase Epitaxy Using Void-Assisted Separation Technology.- Nonpolar and Semipolar GaN Growth by HVPE.- High Growth Rate MOVPE.- Solution Growth Technology.- Ammonothermal Growth of GaN Under Ammono-Basic Conditions.- A Pathway Toward Bulk Growth of GaN by the Ammonothermal Method.- Acidic Ammonothermal Growth Technology for GaN.- Flux Growth Technology.- High Pressure Solution Growth of Gallium Nitride.- A Brief Review on the Na-Flux Method Toward Growth of Large-Size GaN Crystal.- Low Pressure Solution Growth of Gallium Nitride.- Characterization of GaN Crystals.- Optical Properties of GaN Substrates.- Point Defects and Impurities in Bulk GaN Studied by Positron Annihilation Spectroscopy.

Key industries such as the automotive, electronic, medical and laboratory technical industries have continually rising demands for precise manufacturing, handling and control techniques. This is true for the manufacture of injection nozzles for engines as indeed also for the irradiation of extremely fine wafer structures and in the field of scanning probe microscopy. Some examples from research and their industrial application which have been made available by NanoMat Network Partners will be highlighted in this presentation. For example the spontaneous structure formation at the nanoscale and the application as anti-reflection layers.

Silicon carbide is a semiconductor that is highly suitable for various high-temperature and high-power electronic technologies due to its large energy bandgap, thermal conductivity, and breakdown voltage, among other outstanding properties. Large-area high-quality single-crystal wafers are the chief requirement to realize the potential of silicon carbide for these applications. Over the past 20 years, considerable advances have been made in silicon carbide single-crystal growth technology through understanding of growth mechanisms and defect nucleation. Wafer sizes have been greatly improved from wafer diameters of a few millimeters to 100 mm, with overall dislocation densities steadily reducing over the years. Device-killing micropipe defects have almost been eliminated, and the reduction in defect densities has facilitated enhanced understanding of various defect configurations in bulk and homoepitaxial layers. Silicon carbide electronics is expected to continue to grow and steadily replace silicon, particularly for applications under extreme conditions, as higher-quality, lower-priced large wafers become readily available.

In this chapter, research progress of bulk GaN growth by the ammonothermal method at the University of California, Santa Barbara is reviewed. Starting from a fundamental study on chemistry by powder synthesis, ammonothermal GaN growth process has been developed through solubility measurement, growth from metallic Ga nutrient and growth from polycrystalline GaN nutrient. Based on accumulated knowledge on the growth process, polyhedron-shaped GaN bulk crystals were achieved. Future challenges are presented through characterization of GaN wafers sliced from the bulk crystals.

III-nitrides can be grown by employing several different techniques, such as molecular-beam epitaxy (MBE), metalorganic vapor-phase epitaxy (MOVPE), halide vapor-phase epitaxy (HVPE), high-pressure solution growth, and sputtering. Each of these are suited for a particular application; the specific property of HVPE is a much larger growth rate, which makes this technique the natural choice for growth of very thick layers that can be used as high-quality native substrates for subsequent growth of device structures using other techniques. Such substrates will be needed for certain devices with high current density or high voltage load, where the high defect density caused by growth on foreign substrates (heteroepitaxy) cannot be tolerated. The HVPE technology is still under development, and below we present the present situation with emphasis on GaN. The thermodynamic limitations of HVPE growth are discussed first, including the high-temperature chemistry in both the source zone and growth zone of a growth reactor. Examples of the design of growth systems are given; in particular, issues such as flow patterns, parasitic growth, and growth rates are discussed. Methods to reduce the defect density for growth on foreign substrates are discussed, as well as various lift-off techniques to prepare free-standing GaN wafers. Common characterization techniques are mentioned, and important physical properties of high-quality GaN wafers are given. The ongoing developments of HVPE growth for AlN and InN are also briefly summarized.

Crystalline bacterial cell surface layers (S-layers) are key structural components of many bacterial and archaeal cell envelopes. The broad application potential of S-layers in nanobiotechnology is based on specific intrinsic features of the monomolecular arrays which can be split into their constituting subunits and reassembled in suspension or on suitable surfaces (e.g., polymers, metals, silicon wafers) or interfaces (e.g., lipid films, liposomes). S-layers also represent a unique structural basis and patterning element for generating more complex supramolecular structures involving all major classes of biological molecules. Thus, S-layers fulfil key requirements as building blocks and patterning elements for the production of new supramolecular materials and nanoscale devices as required in molecular nanotechnology, nanobiotechnology and biomimetics.

Optical properties of GaN substrates are surveyed to discuss the superiority and critical issues as a substrate for device fabrication. At first, optical properties of a few hundred-micrometer-thick free-standing GaN substrates grown heteroepitaxially on (0001) Al2O3 substrates by metalorganic vapor phase epitaxy and halide vapor phase epitaxy using lateral overgrowth techniques are introduced, as they can also be used as a seed substrate for the ammonothermal overgrowth. Then, spatially-resolved cathodoluminescence (CL) spectra of GaN films grown on free-standing GaN seeds via fluid transport by the ammonothermal method are correlated with the microstructure and growth polarity. The spectral lineshape of local CL was nearly position-independent for a 4-μm-thick N-polar film exhibiting featureless morphology: the spectra exclusively exhibited a broad near-band-edge (NBE) free-carrier recombination emission with Burstein–Moss shift. Conversely, CL spectra at 100 K of a 5-μm-thick Ga-polar film having (10ī1) and (10ī2) facets with ridges originating from central pits exhibited an NBE peak at 3.444 eV and emission bands at 3.27, 2.92, and 2.22 eV, all of which showed rich intensity contrasts in the CL mapping images. The NBE peak intensity was remarkably enhanced at crests of the ridges, where the density of threading dislocations (TDs) having edge components was greatly reduced by the dislocation bending. The results encourage one to grow low TD density GaN wafers by slicing thick crystals grown by the ammonothermal method.

Zinc oxide (ZnO) and gallium nitride (GaN) are wide-bandgap semiconductors with a wide array of applications in optoelectronic and electronics. The lack of low-cost, low-defect ZnO and GaN substrates has slowed development and hampered performance of devices based on these two materials. Their anisotropic crystal structure allows the polar solvents, water and ammonia, to dissolve and crystallize ZnO and GaN at high pressure. Applying the techniques used for hydrothermal production of industrial single-crystal quartz to ZnO and GaN opens a pathway for the inexpensive growth of relatively larger crystals that can be processed into semiconductor wafers. This chapter will focus on the specifics of the hydrothermal growth of ZnO and the ammonothermal growth of GaN, emphasizing requirements for industrial scale growth of large crystals. Phase stability and solubility of hydrothermal ZnO and ammonothermal GaN is covered. Modeling of thermal and fluid flow gradients is discussed and simulations of thermal and temperature profiles in research-grade pressure systems are shown. Growth kinetics for ZnO and GaN respectively are reviewed with special interest in the effects of crystalline anisotropy on thermodynamics and kinetics. Finally, the incorporation of dopants and impurities in ZnO and GaN and how their incorporation modifies electrical and optical properties are discussed.

One of the major drawbacks of transdermal drug delivery (TDD) systems has been their inability to deliver the drugs through the skin at therapeutically desirable range. To overcome this limitation, use of microneedles is gaining popularity. In this paper, the use of microneedles has been proposed for the transdermal drug delivery applications. By using the processes developed by microelectronics industry, the hollow cylindrical silicon microneedles array has been fabricated with microneedles having the tapered tip for easy skin insertion. Mask layout design and fabrication steps involving deep reactive ion etching (DRIE) using silicon wafers is first presented. The process is followed by actual fabrication of silicon hollow microneedles by a series of combined isotropic and anisotropic etching processes using inductively coupled plasma (ICP) etching technology. The performance of the microneedles is numerically characterized by using structural and coupled multifield analysis. To predict the stress distribution and model fluid flow in coupled multifield analysis, finite element (FE) and computational fluid dynamic (CFD) analysis using ANSYS has been used. Flow rate through the microneedles is investigated at different voltages and frequencies using multiple codes coupling method. The analysis of the flow behavior by coupled field method and structural characteristics provides useful data to fabricate optimized design of the hollow silicon microneedle based drug delivery device for transdermal drug delivery applications.

X-ray topography is the general term for a family of x-ray diffraction imaging techniques capable of providing information on the nature and distribution of structural defects such as dislocations, inclusions/precipitates, stacking faults, growth sector boundaries, twins, and low-angle grain boundaries in single-crystal materials. From the first x-ray diffraction image, recorded by Berg in 1931, to the double-crystal technique developed by Bond and Andrus in 1952 and the transmission technique developed by Lang in 1958 through to present-day synchrotron-radiation-based techniques, x-ray topography has evolved into a powerful, nondestructive method for the rapid characterization of large single crystals of a wide range of chemical compositions and physical properties, such as semiconductors, oxides, metals, and organic materials. Different defects are readily identified through interpretation of contrast using well-established kinematical and dynamical theories of x-ray diffraction. This method is capable of imaging extended defects in the entire volume of the crystal and in some cases in wafers with devices fabricated on them. It is well established as an indispensable tool for the development of growth techniques for highly perfect crystals (for, e.g., Czochralski growth of silicon) for semiconductor and electronic applications. The capability of in situ characterization during crystal growth, heat treatment, stress application, device operation, etc. to study the generation, interaction, and propagation of defects makes it a versatile technique to study many materials processes.

Besides the dominant monolithic VLSI integration paradigm, many non-monolithic schemes have already been developed in the past. Typical such schemes include wafer scale integration or multi-reticle wafer, multi-chip module, and 3-D integration. In this chapter we compared these different schemes in a unified cost analysis framework. Our model takes a few parameters extracted from representative fabrication and evaluates the cost efficiency. Our analysis proves that the proposed 2.5-D out significantly outperform other integration paradigms from a cost perspective.