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The semiconductor and hard disk drive industries are investigating nanoimprint for future high volume manufacturing of memory devices and patterned media. Nanoimprint, a form of 1× contact lithography, is one of the few technologies capable of meeting the resolution requirements for next generation electronic and storage devices. Its ability to produce small features with low line width roughness and critical dimension uniformity has been demonstrated by multiple sources. Significant improvements in defectivity have been shown; overlay has improved to within a factor of 2 of that required by the International Technology Roadmap for Semiconductors for 22 nm node flash memory devices; and next generation tools, templates, and processes are being commercialized and tested at end-user sites. Defectivity, throughput, and infrastructure remain as critical challenges, but each has experienced marked improvements in the past year. This technology review and assessment covers critical aspects of nanoimprint for both semiconductor and patterned media manufacturing. It focuses on jet and flash imprint lithography, the type of nanoimprint most often considered for these two applications. The requirements and current status of nanoimprint with respect to high volume manufacturing are presented, and critical aspects are discussed.

The minimum gate pitch for the 65 nm device node will push 193 nm lithography toward k1~0.35 with numerical aperture (NA)=0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65 nm node will be difficult. Lithographers are, therefore, looking into high-transmission attenuated phase shift masks (high-T attPSMs), where T>14%, to improve process margins. The benefits of a high-T attPSM are substantial, but drawbacks like difficulty in inspection, defect free blank manufacture, and sidelobe printing may make the use of such masks impractical. One possible solution to this problem is to employ medium transmission (med-T) attPSM, such as T = 9%, to image critical levels of the 65 nm node with 193 nm lithography. Earlier work has shown that the problems high-T attPSMs face are manageable for med-T attPSM. Sidelobe printing in particular will be treated in this work with simulation and experiment. A primary goal of this effort is to determine if the lithographic benefit of moving from industry-standard 6% attPSM to 9% attPSM is worth the risks associated with such a transition. This goal will be met through a direct comparison of experimental 0.75 NA 193 nm wavelength results for 6% versus 9% attPSM on the gate, contact/via, and metal layers at 65 nm generation target dimensions with leading edge resists.