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This work presents software tools that enable engineers to make relevant SEM measurement decisions in the EDA environment, presented in the optimal context for the engineer, and pass them seamlessly into the SEM environment. We present the tools and interfaces leveraged in this solution and explore the benefits of enabling OPC modeling engineers to make metrology-related decisions within the OPC environment. New opportunities for automation of metrologyrelated OPC tasks are also discussed.

LWR and CD linearity are both a major concern in the interpretation of drawn devices to actual structures on Si, and even more when translating to expected currents (both driven current and leakage current). Both of them have long ago been shown to be sensitive to process (especially lithographic) conditions, but usually not comparatively and, even more seldom are the final (etched) results thus related to the lithography process. Following our previous work on the sensitivities of LER and LWR to layout, we set out to research whether these sensitivities are themselves sensitive to process changes which tend to affect LER and LWR. As a logical conclusion, we expected that process changes which tend to worsen roughness will increase the dependence of the roughness on layout effects - that the outcome will be addible. Measurements were done in Active Area (a.k.a. STI definition) layer. Results show very interesting dependence of roughness and CD linearity (dependence of measured CDs on drawn CDs) of long dense resistors. Process changes that tended to make roughness worse, also had significant impact on the linearity, making it surprisingly more accurate at the low CD regime, but with significantly more variance.

LER (Line Edge Roughness) and LWR (Line Width Roughness) have long been considered a primary issue in process development and monitoring. Development of a low power process flavors emphasizes the effect of LER, LWR on different aspects of the device. Gate level performance, particularly leakage current at the front end of line, resistance and reliability in the back-end layers. Traditionally, as can be seen in many publications, for the front end of line the focus is mainly on Poly and Active area layers. Poly spacers contribution to the gate leakage, for example, is rarely discussed. Following our research on sources of gate leakage, we found leakage current (I off ) in some processes to be highly sensitive to changes in the width of the Poly spacers - even more strongly to the actual Poly gate CDs. Therefore we decided to measure Poly spacers LWR, its correlation to the LWR in the poly, and its sensitivity to changes in layout and OPC. In our last year publication, we defined the terms LLER (Local Line Edge Roughness) and LLWR (Local Line Width Roughness). The local roughness is measured as the 3-sigma value of the line edge/width in a 5-nm segment around the measurement point. We will use these terms in this paper to evaluate the Poly roughness impact on Poly spacer's roughness. A dedicated test chip was designed for the experiments, having various transistors layout configurations with different densities to cover the all range of process design rules. Applied Materials LER and LWR innovative algorithms were used to measure and characterize the spacer roughness relative to the distance from the active edges and from other spaces. To accurately measure all structures in a reasonable time, the recipes were automatically generated from CAD. On silicon, after poly spacers generation, the transistors no longer resemble the Poly layer CAD layout, their morphology is different compared with Photo/Etch traditional structures, and dimensions vary significantly. This paper presents metrology and characterization of poly spacer LLWR and LLER compared to that of the poly gate in various transistor shapes, showing that the relation between them depends on the transistor architecture (final layout, including OPC). It also shows how the spacer deposition may reduce, keep or even enlarge the roughness measured on Poly, depending on transistor layout, but surprisingly, not dependent on proximity effects.

The importance of Line Edge Roughness (LER) and Line Width Roughness (LWR) has long surpassed its effect on process control. As devices scale down, the roughness effects have become a major hindrance for further advancement along Moore’s law. Many studies have been co nducted over the years on the sensitivity of LER to various changes in the materials and the process, which have been c onsidered the main way to tack le the problem – especially through Photoresist improvement. However, despite the incr eased development of DFM tools in recent years, limited research was done as to LER sensitivity to layout, and th e research that was done was limited to proximity effects. In this paper, we study the sensitivity of LER to the layout around the transistor, defined by the gate structure of poly over AA (Active Area). Using different types and geometries of transistors, we found that the poly-gate LER is sensitive to the structure of the Active Area around it (source/dr ain from gate to contact, both shape and length). Using local LER measurement (moving standard deviation of poly edge location), we found a clear correlation between LER value and the length of the AA/STI boundary located at a close range. Longer AA edges yield higher LER, as proved by comparing gate LER of dog-bone transistor with classical transistor. Based on these results, we suggest that LER is sensitive not only to proximity effects, but also to the layout of underlying layers, through the effect of light scattering of the edges during the lithographic process.

A new methodology to predict changes in device performances due to systematic lithography and etch effects is described in this paper. Our methodology consists on Automatic Edge-Contour-Extraction (ECE) on Poly Over Active Layer, taking along the manufacturing variability. In general, the AMAT SEM (Scanning Electron Microscopy) ECE algorithm is based on CAD (GDS) to SEM pattern recognition, followed by CD based 2D edge extraction. Device modeling (using SPICE simulation) is used, to predict the nominal values as well as the device performances variability of the transistors drive current (Ion) and leakage current (Ioff). We used our method to compare a classical (simple rectangular) transistors and "U-Shape AA" transistors, both manufactured using Tower TS013LL (0.13um Low-Leakage) Platform. It was found, as predicted, that U-shape transistors have larger W distribution. However, "U-shape" also showed much tighter L distribution and the overall Ion spread is lower comparing to classical transistors. Also, U-Shape transistors found to have lower Lstdev (gate length distribution of each individual transistor). We also used the ECE methodology, to compare transistors of single side dog-bone to double-side dog-bone. Based on our work, we can predict that single-side dog-bone transistors, will have higher and larger Ioff distributions, and the overall Ioff speared along the wafer, will go up to a factor of x2.5.

In this paper, we study the feasibility of using a new system to set up offline critical dimension scanning electron microscope (CDSEM) recipes for both litho and etch processes monitoring in a foundry environment before first silicon. We will automatically create CDSEM measurement recipes based on CAD design data (2) and litho illumination information. The main advantages of having recipes setup done through this method as compared to performing recipe creation on the CDSEM tool itself are the reduction in CD-SEM tool usage and more importantly, the availability of the recipes before the first wafer is being processed in lithography resulting in a faster of cycle time for new devices. To facilitate our objective, a new feature was implemented in the design to provide a universal global alignment (GA) feature under both optical and SEM view. The global alignment serves two functions: to minimize device-to-device and layer-to-layer optical variation. It synchronizes design (CAD) and wafer coordinate systems. With this universal alignment feature available across all production layers of interest, we can fully automate recipe creation process from design to production.