Search

Line edge roughness (LER) has been widely perceived to be one of the roadblocks to the continuing scaling of semiconductor devices. However, little evidence has been published on the impact of LER on device performance, particularly on the performance and the reliability of advanced interconnects. In this paper, we present such evidence from both the Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) standpoints. In the FEOL, we employed computer simulations to estimate the effects of LER on a number of performance parameters of sub-100nm transistors based on 2-dimensional and 3-dimensional device models. LER has been shown to affect both the average value and the variance of key device performance parameters for sub-100nm transistors. In the BEOL, we investigated the impact of LER on the performance of barrier layers in dual damascene copper interconnects. To this end, we emulated LER by roughening Si surfaces with controlled patterning by self-assembled diblock copolymers and reactive ion etching. In-situ time-resolved X-ray diffraction was used to study Cu diffusion through about 5nm Ta and TaN barrier layers deposited by plasma enhanced-atomic layer deposition (PE-ALD) on both smooth and rough surfaces. The X-ray diffraction results indicated that the surface roughness does not degrade barrier performance of the ALD Cu barriers. Mechanism of the roughness effects is also discussed. Line edge roughness is, however, expected to degrade copper interconnect performance by increasing copper electrical resistivity through enhanced electron surface scattering.