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Minimizing alignment errors in the past has been fairly straightforward. The aim has always been to drive the overlay model correctables to zero either instantly or after a number of lots processed in a short time frame depending on the controller setup. Methods for improving alignment have included minimizing components of variation tied to the exposure tool, metrology tool, process setup, or the model itself. Instead of working on these components, a less expensive alternative for improving the final outcome as represented by the device performance may be not to minimize the overlay correctables but to instead drive to a specific target as defined by the process window around any such correctable. This paper will briefly show that lithography at present geometries is no longer the sole controller of alignment but that in fact other areas such as films, etch, and CMP influence alignment significantly. It will also be shown that in certain instances vertical wafer topography or feature profile may create device asymmetries, which may be compensated partially through application of non-zero overlay correctables. Coping with decreased overlay performance and methodology for controlling overlay biases is also shown.