1. High-precision edge-roughness measurement of transistor gates using three-dimensional electron microscopy combined with marker-assisted image alignment
- Author
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Yuzuru Ohji, Kazuto Ikeda, Mitsuo Ogasawara, Hiroyuki Shinada, Akira Katakami, Shiano Ono, Masanari Koguchi, Hiroshi Kakibayashi, Miyuki Yamane, and Jiro Yugami
- Subjects
Materials science ,business.industry ,Transistor ,3D reconstruction ,Surface finish ,Edge (geometry) ,law.invention ,Optics ,law ,Scanning transmission electron microscopy ,Electron microscope ,business ,Layer (electronics) ,Image resolution - Abstract
We have improved both the spatial resolution and precision of three-dimensional (3D) electron microscopy, which is based on conventional scanning transmission electron microscopy (STEM), by using a micro-pillar specimen together with a 3D analysis holder, and by introducing marker-assisted image alignment prior to 3D reconstruction. Our 3D STEM measurement of aggressively scaled metal-oxide-semiconductor (MOS) gate structures not only successfully showed the z-axis positional dependence of gate-edge profiles and edge-roughness profiles such as line edge roughness (LER) and line width roughness (LWR), but also revealed uniformity of each layer of which the gate structure was composed. Such observations are very important in controlling future device characteristics, but are difficult to obtain using other measurement techniques.
- Published
- 2011