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This paper discusses the integration and development of advanced process control technologies with AMD's Fab25 factory systems using the Advance Process Control Framework. The Framework is an open software architecture that allows the integration of existing factory systems, such as the manufacturing execution systems, configurable equipment interfaces, recipe management systems, metrology tools, process tools, and add-on sensors, into a system which provides advanced process control specific functionality. The Advanced Process Control Framework project was formulated to enable effective integration of Advanced Process Control applications into a semiconductor facility to improve manufacturing productivity and product yields. The main communication link between the factory system and the Framework is the Configurable Equipment Interface. It interfaces through a specialized component in the framework, the Machine Interface, which converts the factory system communication protocol, ISIS, to the Framework protocol, CORBA. The Framework is a distributed architecture that uses CORBA as a communication protocol between specialized components. A generalized example of how the Framework is integrated into the semiconductor facility is provided, as well as a description of the overall architecture used for process control strategy development. The main development language, Tcl/Tk, provides for increased development and deployment over traditional coding methods.

Process faults usually lead to changes in the normal relationship among process variables. These changes can be detected by a Principle Component Analysis (PCA) model based on the data from normal batches of operation. Therefore, monitoring process variables via a PCA model may lead to the earlier detection of process fault than traditional SPC method which depends on periodic information from test wafers. However, PCA is a linear method, and does not explain the relationship among process variables with time. Because the relationship among process variables for a wafer processing equipment is both nonlinear (relationship changes dramatically from one processing step to another) and time dependent (dependent on different processing steps), applying PCA method directly to the monitoring of such processes may prove to be difficult. A multi-PCA modeling technique is proposed in our study of process monitoring and fault detection for a semiconductor manufacturing tool. A series of local PCA models can be built with each local model only describing a local relationship among process variables at a particular time. During monitoring, if an observation from the k th sample of the current run is consistent with the local PCA model built on data around the k th sampling time of previous normal runs, this observation can be considered normal. A method is also proposed to eliminate redundant local PCA models. The proposed method has been implemented for the monitoring of a commercial Rapid Thermal Anneal (RTA) tool. The RTA process is a typical single wafer process. For the same product, all wafers should be processed according to the same recipe. First, the data from normal lots were collected and verified by wafer electrical test (WET) data to be normal data. A multi-PCA model was built based on all data from these normal production lots. In the modeling, only 2 or 3 principal components were necessary for each local PCA model to explain 99% variance of each sub-matrix of data. This paper will discuss using Multi-PCA as a modeling method for detecting real-time process variations based on equipment signals, with abnormal process signals being indicated by a single parameter - Squared Prediction Error (SPE) - from the PCA model. Issues related to the use of this technique in a state-of-the-art semiconductor fab will also be discussed.

For the past few years, both academia and industry have increased research in run-to-run or supervisory level control of semiconductor processes. Run-to-run control has been cited as a necessary and integral part of many current and future leading edge processes. Run-to-run control has been applied or proposed for common and critical fab processes such as chemical mechanical polish (CMP) and lithography/etch line width control. Many traditional as well as advanced control techniques have been used in the formulation of run-to-run controllers (time series and statistical process control- based, state space methods, simple P/PI/PID algorithms, model- based predictive control, etc.). In addition, papers have been published that discuss some of the many issues involved in deploying a run-to-run controller. However, one important issue that affects deployment of run-to-run control has largely been ignored. In many state-of-the-art fabs, especially those that manufacture microprocessors and other logic chips, costly fab tools are required to run more than one process for throughput and flexibility reasons. Furthermore, today's fabs frequently produce more than one type of chip. Both of these factors, multi-processing and - products, sometimes lead to major difficulties in designing and deploying a run-to-run controller This paper focuses on the issues involved in multi-product and -process run-to-run control, as well as compare and contrast some strategies that could be used to design a run-to-run control system under these circumstances.

Iii previous work by Sturtevant et al [1994] it was shown how the use of scatterometry data obtained in real time during the post-expose bake (PEB) step of the photolithography process can improve critical dimension (CD) control. However, it is not obvious that the ad hoc methodology utilized during these experiments conducted at IBM, is the best way to use this valuable information. This paper focuses on the development of more rigorous methods that can incorporate scatterometry data in on-line prediction of the bake time necessary to achieve the target CD. First, a brief description of the system and required tools is given. Then, a model that can relate the measured intensity and the time the wafer has been baked (referred to hereafter as the bake time) is introduced. Then, two theoretical methods that can utilize this model to calculate the bake end point are described. Finally, these two methods are applied to the analysis ofadditional data collected at IBM and operation oftbe complete end point control system is emulated to the extent that is possible. Keywords: end-point detection, process control, deep-UV lithography, scatterometry, post-exposure bake process

The use of a diffraction-based latent image detector during the post-exposure bake (PEB) step for a chemically amplified resist system was investigated and its use in a feedback control strategy was examined. A calibration between intensity of light diffracted from the wafers during PEB and the final post-develop linewidth was determined. Using this relationship, two feedback control strategies were tested. One method altered the PEB time to compensate for unmeasured process disturbances and drive the linewidth to its target. The other method involved altering of the develop time. We found that using the post-exposure bake monitor in a feedback control system can improve wafer-to-wafer and lot-to-lot variability to below that which has been possible through conventional SEM measurements.

Serpentine superlattices (SSL) with a parabolic-crescent cross section defining the wells and barriers, have been grown on vicinal GaAs substrates by molecular beam epitaxy. The SSL structures have been studied by photoluminescence (PL) and photoluminescence excitation (PLE) measurements at 1.4 K, showing a strong polarization anisotropy in both PL and PLE. The carrier confinement has been characterized by measuring the linear polarization dependence of the PL from the surface as well as from the cleaved edges by using a photoelastic modulation technique. Calculations of the conduction band and valence band electronic structure describe the polarization dependence as a function of segregation into lateral wells and barriers. We find that about 30% of the Al intended for the barriers end up in the well giving AlxGa1-xAs wells and barriers of x equals 0.12 and 0.21, instead of the nominally intended values of 0.00 and 0.33, corresponding to a lateral conduction band barrier of 70 meV. Linear polarized PLE has been used to reveal the laterally induced heavy-light hole splitting. PL decay time measurements of the serpentine emission, shows a longer decay time than for a reference alloy-well structure, indicating a reduced carrier relaxation in the serpentine structure. The linear polarization of the PL is found to be rather constant over large areas of the wafer indicating uniform quantum wire like states, showing the intended advantage of the serpentine structure over tilted superlattices.© (1992) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We describe a polarization modulation technique employing a photoelastic modulator and present its implementation in the experimental setup of a photoluminescence (PL) and a photoluminescence excitation (PLE) experiment. In the PL experiment the technique is used to analyze the emitted light with respect to its polarization, whereas for the PLE the polarization of the exciting light is modulated, probing the polarization dependence of the absorption of the light. Since the modulation of the light is restricted to the polarization, the polarization dependence can be measured simultaneously with the PL or PLE intensity. The versatility and the sensitivity of the technique is exemplified by presenting results of polarized PL and PLE obtained on quantum wire samples grown on the vicinal (100) surface of GaAs by molecular beam epitaxy (MBE) that show a considerable anisotropy in the linear polarization for both the PL and PLE at low temperatures.