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In this paper a rapid prototyping design flow is presented and applied to a prototype of the base-band physical layer of a Hiperlan/2 WLAN transceiver. This physical layer is a high performance multi-rate system that contains computationally intensive algorithms. A new method for prototyping the design flow and verifying the process is to use the latest generation of system level design environments (visual data flow environment) for DSPs. The System Generator and Matlab/Simulink tools form a visual data flow environment for FPGA allow us to model DSP systems and explore algorithms. This environment also translates designs into hardware implementations that are faithful, synthesizable and efficient, which can be explored and refined in rapid prototyping platforms.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

In this article we present a study and the corresponding implementation of low cost printed antennas in the 2,4GHz band. These antennas work with low cost transceivers that give a FR input/output signal in the band of interest. The work is part of a project in the field of sensor networks using technology such as Zigbee or even simpler and cheaper systems. We have focused our attention on parameters such as the antenna impedance, which is very important for achieving maximum power transfer with the transceiver while avoiding adaptation circuits. We are also interested in avoiding balums. We have analyzed these printed antennas in terms of their efficiency and radiation pattern using electromagnetic simulation software. Two structures have been evaluated and compared. The first is a structure derived from a monopole and slot antenna and the second is a printed patch antenna.

Design verification methodologies and tool such as DRC and ERC used on MEMS design have been inherited from the transistor based analog and digital full custom design flows. However the devices are defined on a 2D layout, they have a 3D structure. Thus, current tools do not have into account the new features that appear in MEMS design, especially those related with device micro machining. The main consequence on it is that it is necessary to include information of the vertical parameters on the DRC, what is not at all usual in classical design. We claim that the inclusion of such information together with the consequent improvement of tools for DRC, ERC and device parameter extraction, can reduce design and simulation efforts as well as improve the manufacturing yield.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We propose a design and technology methodology and CAD tools for a microsystems fabrication based on the 1.0 micrometers CMOS from ATMEL-ES2. In order to profit from vendor cell libraries, design kits have to be enhanced to deal with the new conception environment. Main contributions are, sensor dependent technology file, device modeling and automatic generation for different ranges, and adaptation of semi- custom tools (simulation environment and P and R) for complete microsystems design. A library of dedicated sensor cells is being designed using Cadence DFWII and the foundry design kit. These sensors are fabricated with the standard CMOS process plus some post-processing steps. Three levels of post-processing are considered: 1) pH-ISFET sensors fabricated using standard CMOS, 2) gas flow and radiation sensors based on thermopiles using simple post-processing. The post-processing is compatible with the foundry CMOS process. Our technology has been developed up tot he point of maximum simplification that results in the use of only one additional mask for back-side etching. Passivation layer together with oxide windows are used for front-side etching with excellent results.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Real-time optical processing is an area of increasing interest in several fields like pattern recognition and inspecting tasks. The development of Spatial Light Modulators (SLMs) capable to display a complex amplitude 2D- distribution in real-time has been very important to obtain real-time optical processors. One of the biggest challenges for improving these processors is to obtain SLMs with a pixel-by-pixel control, which could be easily implemented and fully controlled spatially and with grey-level addressing. Liquid Crystal Displays (LCDs) are inexpensive and suitable SLMs for recognition optical purposes. The LCD panels from the Epson VP100PS videoprojector have been deeply characterized and intensively used as SLMs in optical correlators for pattern recognition. The SLMs can be used in the filter plane as well as in the input plane. If the input image to analyze entails particular requirements in spatial resolution and grey level quantization the response features of the SLM used to display the input image can be critical. In this work we present a full pixel-by-pixel control of the matrix with a PC board. A Field Programmable Gate Array (FPGA) is designed to control a PC board as a prototype to implement a Very Large Scale Integration ASIC driver using the 2.5 microns technology available from the Centro National de Microelectronics (CNM-CSIC, Bellaterra, Spain). The project results in an inexpensive and easy- reconfigurable PC board with the FPGA prototype, and an easy migration to a fully integrated driver of the display.© (1996) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.