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In this work the influence of nanoscale particles caused by processing excursions during back end of line (BEOL) processing on top of the photodiode active region was examined. To investigate the influence of the particles on the photodiode performance, wafer level optical responsivity measurements were done. In addition to the measurements the effect of the particles was simulated with a simplified model based on a modified transfer matrix method (MTMM)1 . The simulation and measurements are in very good agreement with each other and lead to the conclusion that even though some decrease of sensitivity was observed, the overall system variability was reduced by the presence of particles. Furthermore, the influence of the dielectric stack layer thickness variability on the photon flux density is reduced.

The 0.35μm HV-CMOS process technology utilizes several junctions with different doping levels and depths. This process supports complete modular 3V and 5V standard CMOS functionality and offers a wide set of HV transistor types capable for operating voltages from 20V to 120V made available with only 2 more mask adders [1]. Compared to other reported integration of photo detection functionalities in normal CMOS processes [2] or special modified process technologies [3] a much wider variety of junction combinations is already intrinsically available in the investigated technology. Such junctions include beside the standard n+ and p+ source/drain dopings also several combinations of shallow and deep tubs for both p-wells and n-wells. The availability of junction from submicron to 7μm depths enables the selection of appropriate spectral sensitivity ranging from ultraviolet to infrared wavelengths. On the other side by appropriate layouts the contributions of photocurrents of shallower or deeper photo carrier generation can be kept to a minimum. We also show that by analytically modelling the space charge regions of the selected junctions the drift and diffusion carrier contributions can be calculated with a very good match indicating also the suppression of diffusion current contribution. We present examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 380-450nm, 450-600nm or 700-900nm. By appropriate junction choice the ratios of the generated photo currents in their respective peak zones can exhibit more than a factor of 10 compared to the other photo diode combinations. This enables already without further filter implementation a very good spectral resolution for colour sensing applications. Finally the possible junction combinations are also assessed by the achievable dark current for optimized signal to noise characteristic.

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 1•10 12 /cm 3 . In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 4•10 13 /cm 3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100×100μm 2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

IN lithographic processing to define patterns on the high reflective substrate, ARLs (anti-reflective layers) not only enable better line width control but also realize designs that were previously impossible to print. So far, several anti-reflective films like TiN, SiOxNy:H, and organic films for the high reflective substrate have been studied. In this paper, we suggest the novel anti-reflective structure for metal layer patterning, which is Al(aluminum)/SiO 2 stack structure. the reflectivity and the resist absorption rate are simulated for the I-line, and ArF lithography. The simulated thickness of ARL(Al) and ARL(SiO 2 ) for zero reflectivity on the wavelength of 365 nm was 12.6 nm and 95.2 nm respectively, and on the 193 nm was 20.4 nm and 98.8 nm. The process latitude according to the thickness variation of the deposited ARL(Al) and ARL(SiO 2 ) films, and the results of the lithography experiment were discussed.