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As patterning for advanced processes becomes more challenging, designs must become more process-aware. The conventional approach of running lithography simulation on designs to detect process hotspots is prohibitive in terms of runtime for designers, and also requires the release of highly confidential process information. Therefore, a more practical approach is required to make the In-Design process-aware methodology more affordable in terms of maintenance, confidentiality, and runtime. In this study, a pattern-based approach is chosen for Process Hotspot Repair (PHR) because it accurately captures the manufacturability challenges without releasing sensitive process information. Moreover, the pattern-based approach is fast and well integrated in the design flow. Further, this type of approach is very easy to maintain and extend. Once a new process weak pattern has been discovered (caused by Chemical Mechanical Polishing (CMP), etch, lithography, and other process steps), the pattern library can be quickly and easily updated and released to check and fix subsequent designs. This paper presents the pattern matching flow and discusses its advantages. It explains how a pattern library is created from the process weak patterns found on silicon wafers. The paper also discusses the PHR flow that fixes process hotspots in a design, specifically through the use of pattern matching and routing repair.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.