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RTOS based embedded systems are designed with priority based multiple tasks. Inter task communication and data corruptions are major constraints in multi-tasking RTOS system. This study we describe about the solution for these issues with an example Real-time Liquid level control system. Message queue and Mail box are used to perform inter task communication to improve the task execution time and performance of the system. Critical section scheduling is used to eliminate the data corruption. In this application process value monitoring is considered as critical. In critical section the interrupt disable time is the most important specification of a real time kernel. RTOS is used to keep the interrupt disable time to a minimum. The algorithm is studied with respect to task execution time and response of the interrupts. The study also presents the comparative analysis of the system with critical section and without critical section based on the performance metrics.

In this study, the characteristics of DGMOSFET were obtained using mathematical modeling. The variations of characteristics were analyzed with different conditions into consideration. Different parameters behavior is analyzed, such as Transcapacitance variation with the gate voltage, threshold voltage variation with respect to lateral straggle parameter and temperature, mobile charge density variation is also analyzed and also the drain characteristics of the DGMOSFET. The maximum drain current is obtained as 40 mA. The work is done using SPICE simulation software. The results obtained are in greater coherence with previous theoretical investigations.

In SDR, it is advantageous if the data is transmitted using the best among the various modulation techniques with respect to SNR. The receiver has the ability to automatically identify the modulation technique and demodulate it. This process involves a novel method where a pilot sequence helps in identifying the type of modulation at the receiver. Ten modulation techniques are used in this study and their performance is studied. Further, error detection and correction is done to the received data using hamming encoder. This study also discusses about the error handling capability and detection of the position in which the error occurs. This work can be implemented in remote locations and in emergency situations where a particular modulation technique is used based on the available QoS.

This study is about the design and analysis of a reversible logic based multiplexer, that is realized using carbon nano tube transistor. Reversible logic realization of the digital circuits offers numerous advantages over conventional circuit design. Power analysis was performed using HSPICE simulation software and the results are obtained for the 2×1 and 4×1 multiplexer transient behavior. The power consumption is also obtained. Comparative analysis was performed with the conventional CMOS multiiplexer design to validate the proposed design performance.