1. Diffractive Backside Structures via Nanoimprint Lithography
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Benedikt Bläsi, Hubert Hauser, Alexander Mellor, Martin Hermle, Christine Wellens, A. Guttowski, Claas Müller, Jan Benick, and Publica
- Subjects
Amorphous silicon ,Materials science ,Passivation ,Silicon ,chemistry.chemical_element ,02 engineering and technology ,01 natural sciences ,7. Clean energy ,Texturing ,Nanoimprint lithography ,law.invention ,Interference lithography ,010309 optics ,chemistry.chemical_compound ,Optics ,Energy(all) ,law ,0103 physical sciences ,Nanoimprint Lithography ,Wafer ,Silicon oxide ,Light Trapping ,business.industry ,Mikrostrukturierte Oberflächen ,021001 nanoscience & nanotechnology ,Angewandte Optik und funktionale Oberflächen ,Silicium-Photovoltaik ,chemistry ,Optoelectronics ,Photonics ,0210 nano-technology ,business ,Solarthermie und Optik - Abstract
For decreasing thicknesses of wafer based silicon solar cells, photon management structures to maintain high quantum efficiencies will gain importance. Diffractive gratings on the wafer back side can be designed to achieve very high path length enhancements, especially for weakly absorbed infrared radiation. This technologically demanding concept has to be realised using processes with upscaling potential. Therefore, we present a fabrication process for producing photonic structures in silicon based on interference lithography and nanoimprint lithography (NIL). We realised linear as well as crossed gratings of different depths, which were etched into the wafer back side. Polarisation dependent reflection measurements were made to get information about potential absorption enhancement as well as the occurrence of parasitic absorption in the metal reflector. This is conducted for a PECVD silicon oxide buffer layer between grating and reflector as well as a spin coated silicon oxide layer. Besides these optical characterisations, we further investigated the electrical properties of the back surface, where we applied a concept in which electrical and optical properties are decoupled. This is realised by a layer stack on the wafer back side, consisting of a thin Al2O3 passivation and a doped amorphous silicon layer.
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