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In order to obtain high-quality through-silicon via (TSV) arrays for high voltage applications, we optimized the fabrication processes of the Si holes, evaluated the dielectric layers, carried out hole filling by Cu plating, and detected the final structure and electric properties of the TSVs. The Si through-hole array was fabricated in an 8-inch Si substrate as follows: First, a blind Si hole array was formed by the Si deep reactive etching (DRIE) technique using the Bosch process, but with the largest width of the top scallops reduced to 540 nm and the largest notch elimidiameternated by backside grinding, which also opens the bottom ends of the Si blind holes and forms 500-μm-deep Si through holes. Then, the sidewalls of the Si holes were further smoothed by a combination of thermal oxidation and wet etching of the thermal oxide. The insulating capability of the dielectric layers was evaluated prior to metal filling by using a test kit. The metal filling of the through holes was carried out by bottom-up Cu electroplating and followed by annealing at 300 °C for 1 h to release the electroplating stress and to prevent possible large metal thermal expansion in subsequent high-temperature processes. The TSV arrays with different hole diameters and spacing were detected: no visible defects or structure peeling was found by scanning electron microscopy (SEM) observations, and no detectable interdiffusion between Cu and the dielectric layers was detected by energy dispersive X-ray (EDX) analyses. Electric tests indicated that the leakage currents between two adjacent TSVs were as low as 6.80 × 10−10 A when a DC voltage was ramped up from 0 to 350 V, and 2.86 × 10−9 A after a DC voltage was kept at 100 V for 200 s.

This paper presents a simple and reliable routine for batch fabrication of wear-resistant and conductive probe with a PtSi tip. The fabrication process is based on inductively coupled plasma (ICP) etching, metal evaporation, and annealing. Si tips with curvature radii less than 10 nm were produced with good wafer-level uniformity using isotropic etching and thermal oxygen sharpening. The surface roughness of the etched tip post was reduced by optimized isotropic etching. The dependence of the platinum silicide morphology on annealing conditions were also systematically investigated, and conductive and wear-resistant probes with PtSi tips of curvature radii less than 30 nm were batch fabricated and applied for scanning piezoelectric samples.

A novel microcantilever sensor was batch fabricated for Yersinia detection. The microcantilever surface modification method was optimized by introducing a secondary antibody to increase the number of binding sites. A novel microfluidic platform was designed and fabricated successfully. A 30 &mu, L solution could fully react with the microcantilever surface. Those routines enhanced the binding efficiency between the target and receptor on the microcantilever. With this novel designed microfluidic platform, the specific adsorption of 107 Yersinia on the beam surface with modified F1 antibody was significantly enhanced.