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As the demand for high-density, high-performance technologies in semiconductor systems increases, efforts are being made to mitigate and optimize the issues of high current density and heat generation within interconnects to ensure reliability. While interconnects are the most fundamental pathways for transmitting current signals, there has been relatively little research conducted on them compared to individual unit devices from the perspective of overall system performance. However, as integration density increases, the amount of loss in interconnects also rises, necessitating research and development to minimize these losses. In this study, we propose a method to analyze power efficiency by utilizing the differences between simulation results and measured results of interconnect structures. We confirmed that the difference between theoretical resistance values and actual measured values varies with the contact area ratio between metal lines and vias, and we analyzed the power efficiency based on these differences. Using the findings, we proposed and validated a structure that can improve power efficiency. This study presents a method to analyze power efficiency and suggests ways to achieve higher power efficiency within the limited specifications of interconnects. This contributes to enhancing power efficiency and ensuring reliability, thereby preserving the performance of the overall system in highly integrated semiconductor systems.

With the recent rapid development of IT technology, the demand for multifunctional semiconductor devices capable of high performance has increased rapidly, and the miniaturization of such devices has also faced limitations. To overcome these limitations, various studies have investigated three-dimensional packaging methods of stacking devices, and among them, hybrid bonding is being actively conducted during the bonding process. studies of hybrid bonding during the bonding process are active. In this study, Cu bonding using a nano passivation layer was carried out for Cu/SiO2 hybrid bonding applications, with Au and Ag deposited on Cu at the nano level and used as a protective layer to prevent Cu oxidation and to achieve low-temperature Cu bonding. Au was deposited at about 12 nm, and Ag was deposited at about 15 nm, with Cu bonding carried out at 180 °C for 30 min, after which an annealing process was conducted at 200 °C for one hour. After bonding, the specimen was diced into a 1 cm × 1 cm chip, and the bonding interface was analyzed using SEM and TEM. Additionally, the 1 cm × 1 cm chip was diced into 2 mm × 2 mm specimens to measure the shear strength of the bonded chip, and the average shear strength of Au and Ag was found to be 5.4 and 6.6 MPa, respectively. The degree of diffusion between Au-Cu and Ag-Cu was then investigated; the diffusion activation energy when Au diffuses to Cu was 6369.52 J/mol, and the diffusion activation energy when Ag diffuses to Cu was 17,933.21 J/mol.

The size of the memory market is expected to continue to expand due to the digital transformation triggered by the fourth industrial revolution. Among various types of memory, NAND flash memory has established itself as a major data storage medium based on excellent cell characteristics and manufacturability; as such, the demand for increasing the bit density and the performance has been rapidly increasing. In this paper, we will review the device operation algorithm and techniques to improve the cell characteristics and reliability in terms of optimization of individual program, read and erase operation, and system level performance.

Low-temperature Cu-Cu bonding technology plays a key role in high-density and high-performance 3D interconnects. Despite the advantages of good electrical and thermal conductivity and the potential for fine pitch patterns, Cu bonding is vulnerable to oxidation and the high temperature of the bonding process. In this study, chip-level Cu bonding using an Ag nanofilm at 150 °C and 180 °C was studied in air, and the effect of the Ag nanofilm was investigated. A 15-nm Ag nanofilm prevented Cu oxidation prior to the Cu bonding process in air. In the bonding process, Cu diffused rapidly to the bonding interface and pure Cu-Cu bonding occurred. However, some Ag was observed at the bonding interface due to the short bonding time of 30 min in the absence of annealing. The shear strength of the Cu/Ag-Ag/Cu bonding interface was measured to be about 23.27 MPa, with some Ag remaining at the interface. This study demonstrated the good bonding quality of Cu bonding using an Ag nanofilm at 150 °C.

The technology trends of next generation electronic packaging are moving toward heterogeneous 3D packaging systems. One of the key processes of 3D packaging system is Cu-to-Cu bonding, which is highly dependent on the planarized, activated, and oxygen-free Cu surface. A two-step plasma treatment is studied to form a Cu surface that does not react with oxygen and improves the Cu bonding interface quality at low bonding temperature (300 °C). In this study, the effects of two-step plasma treatment on both sputtered and electroplated Cu surfaces were evaluated through structural, chemical, and electrical analysis. The Cu bonding interface was studied by scanning acoustic tomography analysis after the thermocompression bonding process. Both sputtered and electroplated Cu thin films had the preferred orientation of (111) plane, but sputtered Cu exhibited larger grains than the electroplated Cu. As a result, the roughness of sputtered Cu was lower, and the resistivity was higher than that of electroplated Cu. Based on X-ray photoelectron spectroscopy analysis, the sputtered Cu formed more copper nitrides and fewer copper oxides than the electroplated Cu. A significant improvement in bonding quality at the Cu bonded interface was observed in sputtered Cu.