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In order to address the inconsistency problem caused by parasitic backend wiring among multiple ramp generators and among multiple columns in large-array CMOS image sensors (CIS), this paper proposes a high-precision compensation technology combining average voltage technology, adaptive negative feedback dynamic adjustment technology, and digital correlation double sampling technology to complete the design of an adaptive ramp signals inconsistency calibration scheme. The method proposed in this article has been successfully applied to a CIS with a pixel array of 8192(H) × 8192(V), based on the 55 nm 1P4M CMOS process, with a pixel size of 10×10μm2. The chip area is 88(H) × 89(V) mm2, and the frame rate is 10 fps. The column-level analog-to-digital converter is a 12-bit single-slope analog-to-digital converter (SS ADC). The experimental results show that the ramp generation circuit proposed in this paper can reduce the inconsistency among the ramp signals to 0.4% LSB, decreases the column fixed pattern noise (CFPN) caused by inconsistent ramps of each column to 0.000037% (0.15 e−), and increases the overall chip area and power consumption by only 0.6% and 0.5%, respectively. This method provides an effective solution to the influence of non-ideal factors on the consistency of ramp signals in large area array CIS.

This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally, SEUs are considered to have negative effects on electronic systems or designs, but the current study demonstrates that they can also have positive contributions to the DNN on the MPSoC. The assertion that SEUs can have positive contributions to electronic system design was supported by conducting fault injections through dynamic reconfiguration on DNNs implemented on a 16nm FinFET technology Zynq UltraScale+ MPSoC. The results of the current study were highly significant, indicating that an SEU in configuration memory could result in an impressive 8.72% enhancement in DNN recognition on the MPSoC. One possible cause is that SEU in the configuration memory leads to slight changes in weight or bias values, resulting in improved activation levels of neurons and enhanced final recognition accuracy. This discovery offers a flexible and effective solution for boosting DNN performance on the MPSoC platform.

Silicon photonics (SiPh) has emerged as a promising technology for photonic integrated circuits (PICs). One of the basic components in SiPh is the directional coupler (DC), which plays an important role in signal monitoring with the requirement of low wavelength dependence and low loss. This paper proposes a broadband and low-loss DC designed for signal power tapping on the 3 μm silicon-on-insulator (SOI) waveguide platform. By utilizing the advantages of multi-micron waveguides and replacing one of the straight waveguides with an optimized arc-shaped waveguide in the coupling region, the proposed DC enhances spectral stability and improves transmission with negligible loss. Experimental evidence indicates that the proposed DC showcases a minimal variation in the tapping ratio. From 1470 nm to 1630 nm, the largest deviation away from the tapping ratio at 1550 nm is 1.433%. Additionally, the device exhibits a low excess loss of −0.27 dB. These results suggest that the proposed device is well-suited to reliable signal power tapping and monitoring, particularly within PICs.

With the rapid development of autonomous driving technology, future road traffic must be composed of autonomous vehicles and artificial vehicles. Although autonomous vehicles have greatly improved road capacity, few studies have involved capacity at signal-controlled intersections, and most of the studies are based on experimental simulation. As such, there is a need to more scientifically analyze the impact of autonomous vehicles on road and intersection capacity. Based on three theories of flow-density relationships, traffic flow equilibrium analysis, and the following model, this paper firstly deduces the flow-density relationship of different vehicle types in a single environment. Secondly, flow-density relationships under different proportions of self-driving vehicles are derived. Through the derivation of these two models, the basic road saturation flow rates under different permeabilities of self-driving vehicles, can be obtained. Based on these results, a revised calculation model for the capacity of signalized intersections with different proportions of autonomous vehicles is proposed, which is essentially to revise the basic saturation flow rate under different permeabilities of autonomous vehicles. By using SUMO 1.15.0 traffic simulation software, the theoretical models are individually tested. The results show that the error rate between the theoretical calculation results and the SUMO simulation results, is less than 16%. This study can provide a basis for the calculation of basic capacity of roads and intersections in a future man-machine hybrid driving environment, and provide theoretical guidance for traffic management and control.

In this work, a vertical N-I-P germanium (Ge) photodetector (PD) with a multi-mode waveguide input is presented. The fabricated devices exhibit a low dark current of 10 nA at bias of −1 V, and a high responsivity of exceeding 0.75 A/W over the wavelength range from 1270 to 1350 nm. High-frequency characteristics measurements show that the photodetector has a 3 dB opto-electrical (OE) bandwidth of 23 GHz under −3 V bias, which can be further improved by optimization of the photodetector configuration. A 50 Gb/s clear eye diagram with a non-return-to-zero (NRZ) modulation format is demonstrated. By using a single-mode excitation source, which is used to simulate light coming from the wavelength division multiplexing (WDM) devices, and sweeping its position, it is shown that the multi-mode input photodetector can be utilized in a WDM receiver to achieve both high responsivity and a flat-top passband.

In this paper, a 7.75 kHz line rate analog domain time delay integration (TDI) CMOS analog accumulator with 128-stage is proposed. An adaptive compensation for the charge loss due to parasitic effects is adopted. Based on the influence mechanism of parasitic effects, alternately charging the top and bottom plates of the storage capacitor while cooperate positive feedback capacitor dynamically compensates for the charge loss of the sampling phase and the holding phase. Using the proposed circuit, after the post-layout simulation verification, the SNR of 128 stage accumulation can be improved by as much as 20.9 dB.

For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.