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The rapid development of digitalization has introduced greater variability and trust-related risks to the banking industry. Enhancing customers' perception of value co-creation with banks is a critical issue that requires attention. This study aims to explore the impact and mechanism of a bank's social responsibility practices on its customers' value co-creation in the digital context. A cross-level analysis model was developed and analyzed based on in-depth surveys of 30 bank managers and 262 valid customers. The results reveal that (1) CSR practices have no impact on customer value co-creation in the digital context; (2) CSR practices have a positive impact on customers' perception of a company's social responsibility; (3) customers' perception of a company's social responsibility has a positive impact on customer value co-creation; and (4) customers' perception plays a mediating role between CSR practices and customer value co-creation. Although corporate social responsibility is becoming increasingly important in the current digital economy, our study found that it does not necessarily lead to more customer value co-creation. Banks must enable customers to perceive their CSR practices in order to foster value co-creation. This study has important implications for banking practitioners seeking to strengthen their social responsibility practices and create value with their customers in the digital era. [ABSTRACT FROM AUTHOR]

A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design. [ABSTRACT FROM AUTHOR]